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    Integrated circuit memory devices including transmission parts that are adjacent input/output selection parts
    31.
    发明授权
    Integrated circuit memory devices including transmission parts that are adjacent input/output selection parts 有权
    集成电路存储器件包括相邻输入/输出选择部件的传输部件

    公开(公告)号：US06396756B1

    公开(公告)日：2002-05-28

    申请号：US09684190

    申请日：2000-10-06

    Applicant: Sang-Seok Kang ,  Jae-Hoon Joo ,  Young-Ok Cho

    Inventor： Sang-Seok Kang ,  Jae-Hoon Joo ,  Young-Ok Cho

    IPC: G11C700

    CPC classification number: G11C11/4096

    Abstract: Integrated circuit memory devices include first and second memory cell arrays, first and second transmission parts between the first and second memory cell arrays, and first and second input/output selection parts between the first and second memory cell arrays, wherein the first transmission part is adjacent the first input/output selection part and wherein the second transmission part is adjacent the second input/output selection part. A transistor in the first transmission part and a transistor in the first input/output selection part can share a first common source/drain region. A transistor in the second transmission part and a transistor in the second input/output selection part also can share a second common source/drain region. First and second input/output selection parts also may be provided between the first and second transmission parts. At least one sense amplifier part may be provided between the first and second input/output selection parts.

    Abstract translation: 集成电路存储器件包括第一和第二存储单元阵列，第一和第二存储单元阵列之间的第一和第二传输部分以及第一和第二存储单元阵列之间的第一和第二输入/输出选择部分，其中第一传输部分 邻近第一输入/输出选择部分，并且其中第二传输部分与第二输入/输出选择部分相邻。 第一传输部分中的晶体管和第一输入/输出选择部分中的晶体管可以共享第一公共源极/漏极区域。 第二传输部分中的晶体管和第二输入/输出选择部分中的晶体管也可以共享第二公共源极/漏极区域。 也可以在第一和第二传动部件之间设置第一和第二输入/输出选择部件。 可以在第一和第二输入/输出选择部分之间提供至少一个读出放大器部分。

    Multi-bank integrated circuit memory devices having cross-coupled isolation and precharge circuits therein
    32.
    发明授权
    Multi-bank integrated circuit memory devices having cross-coupled isolation and precharge circuits therein 有权
    在其中具有交叉耦合隔离和预充电电路的多存储体集成电路存储器件

    公开(公告)号：US6028797A

    公开(公告)日：2000-02-22

    申请号：US196991

    申请日：1998-11-20

    Applicant: Gwang-young Kim ,  Jong-hyoung Lim ,  Sang-seok Kang

    Inventor： Gwang-young Kim ,  Jong-hyoung Lim ,  Sang-seok Kang

    IPC: G11C11/41 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/34 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00

    CPC classification number: G11C7/1042 ,  G11C7/06 ,  G11C7/12 ,  G11C2207/12

    Abstract: Multi-bank integrated circuit memory devices include first and second memory cell arrays having first and second pairs of differential bit lines electrically coupled thereto, respectively. A dual sense amplifier is also provided and this sense amplifier is electrically coupled together by a first pair of differential input/output lines. First and second isolation circuits are also provided. The first isolation circuit is electrically coupled to the first pair of differential bit lines and is responsive to a first control signal (C1). The second isolation circuit is electrically coupled to the second pair of differential bit lines and is responsive to a second control signal (C2). First and second equalization circuits are provided. The first equalization circuit is responsive to the second control signal and performs the function of equalizing a potential of the first pair of differential bit lines. The second equalization circuit is responsive to the first control signal and performs the function of equalizing a potential of the second pair of differential bit lines. These first and second control signals are generated by a control signal generator, in response to a row address.

    Abstract translation: 多组集成电路存储器件包括分别与其电耦合的第一和第二对差分位线的第一和第二存储单元阵列。 还提供双重放大器，并且该读出放大器通过第一对差分输入/输出线电耦合在一起。 还提供了第一和第二隔离电路。 第一隔离电路电耦合到第一对差分位线，并响应于第一控制信号（C1）。 第二隔离电路电耦合到第二对差分位线，并响应于第二控制信号（C2）。 提供第一和第二均衡电路。 第一均衡电路响应于第二控制信号，并且执行均衡第一对差分位线的电位的功能。 第二均衡电路响应于第一控制信号，并且执行均衡第二对差分位线的电位的功能。 响应于行地址，这些第一和第二控制信号由控制信号发生器产生。

    SEMICONDUCTOR MEMORY MODULE AND DEVICE HAVING POWER MANAGEMENT UNIT
    34.
    发明公开
    SEMICONDUCTOR MEMORY MODULE AND DEVICE HAVING POWER MANAGEMENT UNIT 审中-公开

    公开(公告)号：US20230298658A1

    公开(公告)日：2023-09-21

    申请号：US18010402

    申请日：2021-11-22

    Applicant: Sung Yun RYU ,  Sang Seok KANG ,  JM SEMICONDUCTOR.CO., LTD.

    Inventor： Sung Yun RYU ,  Sang Seok KANG

    IPC: G11C11/4074

    CPC classification number: G11C11/4074

    Abstract: The disclosure relates to a semiconductor memory device including a semiconductor memory module and a semiconductor memory control unit, and since the semiconductor memory module includes a power management unit, and the power management unit generates a reference voltage and various internal voltages to be supplied to a dynamic random access memory (DRAM) chip array, and receives the internal voltages supplied to the DRAM chip array by feedback to measure and compensate the internal voltages, a stable and accurate voltage can be supplied to the DRAM chip array.

    Semiconductor memory device for self refresh and memory system having the same
    35.
    发明授权
    Semiconductor memory device for self refresh and memory system having the same 有权
    具有其自刷新和存储系统的半导体存储器件

    公开(公告)号：US08144539B2

    公开(公告)日：2012-03-27

    申请号：US12645962

    申请日：2009-12-23

    Applicant: Jong Hyoung Lim ,  Sang Seok Kang

    Inventor： Jong Hyoung Lim ,  Sang Seok Kang

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C11/40615

    Abstract: A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle.

    Abstract translation: 一种半导体存储器件包括：存储器核心单元，包括具有多个存储单元的存储单元阵列和用于感测和放大多个存储单元的数据的读出放大器;以及自刷新控制单元，用于施加至少一个第一核心电压 并且在第一自刷新模式下，在第一自刷新周期中控制自刷新操作，并且将至少一个第二核心电压施加到存储器核心单元并且控制自刷新操作 在第二自刷新模式下在每第二自刷新循环中执行。 在半导体存储器中，所述至少一个第一核心电压的电平高于所述至少一个第二核心电压中相应的第一核心电压的电平，并且所述第一自刷新周期比所述第二自刷新周期短。

    FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME
    36.
    发明申请
    FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME 失效
    保险丝电路和具有相同功能的半导体器件

    公开(公告)号：US20110188334A1

    公开(公告)日：2011-08-04

    申请号：US13020450

    申请日：2011-02-03

    Applicant: Sang-Seok KANG ,  Sang-Man BYUN ,  Jae-Hoon JOO

    Inventor： Sang-Seok KANG ,  Sang-Man BYUN ,  Jae-Hoon JOO

    IPC: G11C5/14 ,  H01H37/76

    CPC classification number: G11C5/14 ,  H01H37/76

    Abstract: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

    Abstract translation: 提供了能够根据操作模式选择性地使用用于逻辑运算的电源电压的熔丝电路。 熔丝电路包括模式产生电路，电源电压选择电路和至少一个保险丝单元。 模式产生电路产生多个模式信号。 电源电压选择电路响应于多个模式信号选择多个电源电压中的一个，并将所选择的电源电压输出到第一节点。 每个熔丝单元耦合在第一节点和地电压之间，并且使用所选择的电源电压作为用于逻辑运算的电源电压。 因此，包括熔丝电路的半导体装置可以精确地测试熔丝的连接状态。

    Semiconductor memory device including on die termination circuit and on die termination method thereof
    37.
    发明授权
    Semiconductor memory device including on die termination circuit and on die termination method thereof 失效
    半导体存储器件包括管芯端接电路及其管芯端接方法

    公开(公告)号：US07675316B2

    公开(公告)日：2010-03-09

    申请号：US11429365

    申请日：2006-05-05

    Applicant: Jong-Hyoung Lim ,  Sang-Seok Kang

    Inventor： Jong-Hyoung Lim ,  Sang-Seok Kang

    IPC: H03K17/16

    CPC classification number: G11C7/1078 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084

    Abstract: A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.

    Abstract translation: 提供半导体存储器件。 该器件包括通过检测通过焊盘输入的信号的相位变化来控制终端电阻值的芯片上终端电路。 此外，当在时钟信号的n（n为正整数）周期期间输入相同的相位信号时，导线端接电路改变终端电阻值。

    Semiconductor memory device and method thereof
    39.
    发明申请
    Semiconductor memory device and method thereof 有权
    半导体存储器件及其方法

    公开(公告)号：US20080052567A1

    公开(公告)日：2008-02-28

    申请号：US11730273

    申请日：2007-03-30

    Applicant: Jong-Hyoung Lim ,  Sang-Seok Kang

    Inventor： Jong-Hyoung Lim ,  Sang-Seok Kang

    IPC: G11C29/00

    CPC classification number: G11C7/1078 ,  G11C7/1006 ,  G11C7/1096 ,  G11C11/4096

    Abstract: A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.

    Abstract translation: 提供一种半导体存储器件及其方法。 示例性方法可以涉及在半导体存储器件中执行存储器操作，并且可以包括接收对应于所接收的数据的至少一部分的数据和数据屏蔽信号，响应于 写入命令和数据屏蔽信号，被配置为阻止所接收的数据的至少一部分被写入到存储器中，并且针对每个接收的数据和数据屏蔽信号配置不同的定时参数，从而执行写入命令而没有 将所接收的数据的至少一部分写入存储器。

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