公开(公告)号：US07553732B1

公开(公告)日：2009-06-30

申请号：US11150923

申请日：2005-06-13

Applicant: David E. Brown ,  Scott D. Luning

Inventor： David E. Brown ,  Scott D. Luning

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

Abstract: A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

Abstract translation: 提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。 该方法适用于集成到集成电路半导体器件的制造工艺中。 该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。

公开(公告)号：US20090008718A1

公开(公告)日：2009-01-08

申请号：US12199659

申请日：2008-08-27

Applicant: Gen PEI ,  Scott D. LUNING ,  Johannes van MEER

Inventor： Gen PEI ,  Scott D. LUNING ,  Johannes van MEER

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/7843

Abstract: A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

Abstract translation: 提供了一种CMOS电路，其包括PMOS晶体管，在沟道宽度方向上与PMOS晶体管相邻的NMOS晶体管，覆盖PMOS晶体管的压应力衬垫以及覆盖NMOS晶体管的拉伸应力衬垫。 压缩应力衬垫的一部分和拉伸应力衬垫的一部分处于堆叠构型，并且压应力衬垫和拉伸应力衬垫的重叠区域足以导致压缩应力衬垫中的增强的横向应力或 拉伸应力衬垫。

公开(公告)号：US06743685B1

公开(公告)日：2004-06-01

申请号：US09784629

申请日：2001-02-15

Applicant: David D. Wu ,  Michael P. Duane ,  Scott D. Luning

Inventor： David D. Wu ,  Michael P. Duane ,  Scott D. Luning

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/26586 ,  H01L21/28202 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66492 ,  H01L29/7833

Abstract: A method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the cage region of the doped-poly gate structure adjacent the gate dielectric.

Abstract translation: 提供了一种方法，所述方法包括在衬底的表面上形成栅极电介质，并在栅极电介质上方形成掺杂多晶硅栅极结构，所述掺杂 - 多晶硅结构具有边缘区域。 该方法还包括在与栅极电介质相邻的掺杂多晶硅栅极结构的笼状区域中形成掺杂剂贫化多晶硅区域。

公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

Applicant: Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

Inventor： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/66825

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US20090267152A1

公开(公告)日：2009-10-29

申请号：US12496133

申请日：2009-07-01

Applicant: Paul R. Besser ,  Scott D. Luning

Inventor： Paul R. Besser ,  Scott D. Luning

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66772

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract translation: 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US06787464B1

公开(公告)日：2004-09-07

申请号：US10189048

申请日：2002-07-02

Applicant: Jon D. Cheek ,  Scott D. Luning

Inventor： Jon D. Cheek ,  Scott D. Luning

IPC: H01L2144

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/7833

Abstract: The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of at least a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors. In yet another illustrative embodiment, the method comprises forming a layer of refractory metal to an original thickness above a plurality of transistors, reducing the original thickness of a portion of the layer of refractory metal above at least some of the transistors to define a layer of refractory metal having multiple thicknesses, and performing at least one anneal process to convert portions of the layer of refractory metal having multiple thicknesses to metal silicide regions on the transistors.

Abstract translation: 本发明一般涉及基于栅极临界尺寸在晶体管上形成金属硅化物区域的各种方法。 在一个说明性实施例中，该方法包括在多个晶体管上形成难熔金属层，减少至少部分晶体管的至少一部分难熔金属的厚度，并执行至少一个退火工艺以形成 晶体管上方的金属硅化物区域。 在另一示例性实施例中，该方法包括在多个晶体管上方形成难熔金属层，减小了具有栅极电极的第一晶体管之上的难熔金属层的厚度，临界尺寸小于临界尺寸 的多个晶体管中的另一个晶体管的栅极电极结构，并且执行至少一个退火工艺以在所述多个晶体管上形成金属硅化物区域。 在另一个说明性实施例中，该方法包括在多个晶体管上方形成原始厚度的难熔金属层，将难熔金属层的一部分的一部分的原始厚度减小到至少一些晶体管之上以限定一层 具有多个厚度的难熔金属，并且执行至少一个退火工艺以将具有多个厚度的难熔金属层的部分转换成晶体管上的金属硅化物区域。

公开(公告)号：US06624035B1

公开(公告)日：2003-09-23

申请号：US09523631

申请日：2000-03-13

Applicant: Scott D. Luning ,  David Donggang Wu ,  Massud Aminpur

Inventor： Scott D. Luning ,  David Donggang Wu ,  Massud Aminpur

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586

Abstract: The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a surface of a semiconducting substrate, and forming a hard mask layer above the gate electrode and the substrate. The method further comprises patterning the hard mask layer to define an opening in the hard mask layer, and performing an angled implantation process through the opening in the hard mask to introduce dopant atoms into the substrate under at least a portion of the gate electrode.

Abstract translation: 本发明涉及一种在半导体器件中形成晕轮植入物的方法。 在一个说明性实施例中，该方法包括在半导体衬底的表面上方形成栅电极，以及在栅电极和衬底上形成硬掩模层。 该方法还包括图案化硬掩模层以在硬掩模层中限定开口，以及通过硬掩模中的开口进行成角度的注入工艺，以在栅电极的至少一部分下将掺杂剂原子引入衬底中。

公开(公告)号：US06391751B1

公开(公告)日：2002-05-21

申请号：US09626668

申请日：2000-07-27

Applicant: David Donggang Wu ,  William R. Roche ,  Scott D. Luning ,  Karen L. E. Turnqest

Inventor： David Donggang Wu ,  William R. Roche ,  Scott D. Luning ,  Karen L. E. Turnqest

IPC: H01L23205

CPC classification number: H01L21/28123

Abstract: The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon, forming a masking layer above the layer of polysilicon, and patterning the masking layer to expose portions of the layer of polysilicon. The method further comprises implanting a dopant material into the exposed portions of the layer of polysilicon to convert the exposed portions of the layer of polysilicon to substantially amorphous silicon, and performing an etching process to remove the substantially amorphous silicon to define a gate electrode.

Abstract translation: 本发明涉及一种形成半导体器件的方法。 在一个说明性实施例中，该方法包括形成多晶硅层，在多晶硅层上形成掩模层，以及图案化掩模层以暴露多晶硅层的部分。 该方法还包括将掺杂剂材料注入到多晶硅层的暴露部分中以将多晶硅层的暴露部分转变为基本上非晶硅，并执行蚀刻工艺以去除基本上非晶硅以限定栅​​电极。

公开(公告)号：US06387755B1

公开(公告)日：2002-05-14

申请号：US08992616

申请日：1997-12-17

Applicant: Timothy J. Thurgate ,  Scott D. Luning

Inventor： Timothy J. Thurgate ,  Scott D. Luning

IPC: H01L21336

CPC classification number: H01L29/66825

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. The method and system include providing an oxide layer on the semiconductor and providing at least one gate stack disposed above the oxide layer. The at least one gate stack has a corner contacting the oxide layer. The method and system further include exposing at least the corner of the at least one gate stack and rounding at least the corner of the at least one gate stack.

Abstract translation: 公开了一种在半导体上提供存储单元的系统和方法。 该方法和系统包括在半导体上提供氧化物层并提供设置在氧化物层上方的至少一个栅极堆叠。 至少一个栅极堆叠具有与氧化物层接触的拐角。 所述方法和系统还包括至少暴露所述至少一个栅极堆叠的角部并至少对所述至少一个栅极叠层的角进行舍入。

公开(公告)号：US06372587B1

公开(公告)日：2002-04-16

申请号：US09568069

申请日：2000-05-10

Applicant: Jon D. Cheek ,  Scott D. Luning ,  Derick J. Wristers

Inventor： Jon D. Cheek ,  Scott D. Luning ,  Derick J. Wristers

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness &tgr; above the surface and having an edge disposed a distance &dgr; from the first edge of the structure. The method also includes implanting the halo implant at an angle &agr; with respect to a direction perpendicular to the surface, wherein the tangent of the angle &agr; is at least the ratio of the distance &dgr; to the thickness &tgr;.

Abstract translation: 提供了一种用于在邻近结构的一侧的衬底中形成卤素注入的方法，所述方法包括在所述衬底的表面上方形成所述结构，所述结构具有第一和第二边缘并且形成限定邻近所述结构的区域的掩模， 该面具具有厚度＆tgr; 并且具有与结构的第一边缘相距一定距离的边缘。 该方法还包括将晕圈植入物相对于垂直于该表面的方向以角度α注入，其中角度α的切线至少为距离δ与厚度的比值。