公开(公告)号：US20090236664A1

公开(公告)日：2009-09-24

申请号：US12471600

申请日：2009-05-26

申请人： David E. Brown ,  Scott D. Luning

发明人： David E. Brown ,  Scott D. Luning

IPC分类号： H01L29/786

CPC分类号： H01L29/66545 ,  H01L21/0206 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

摘要： A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

摘要翻译： 提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。 该方法适用于集成到集成电路半导体器件的制造工艺中。 该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。

公开(公告)号：US07553732B1

公开(公告)日：2009-06-30

申请号：US11150923

申请日：2005-06-13

申请人： David E. Brown ,  Scott D. Luning

发明人： David E. Brown ,  Scott D. Luning

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/0206 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

摘要： A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

摘要翻译： 提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。 该方法适用于集成到集成电路半导体器件的制造工艺中。 该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。

公开(公告)号：US06506642B1

公开(公告)日：2003-01-14

申请号：US10020931

申请日：2001-12-19

申请人： Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

发明人： Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

IPC分类号： H01L218238

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656

摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.

摘要翻译： 亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。 实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物， 在栅电极的已经被去除了第一侧壁间隔物的侧表面上。 实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。

公开(公告)号：US07910996B2

公开(公告)日：2011-03-22

申请号：US12496133

申请日：2009-07-01

申请人： Paul R. Besser ,  Scott D. Luning

发明人： Paul R. Besser ,  Scott D. Luning

IPC分类号： H01L29/12

CPC分类号： H01L29/66628 ,  H01L29/66772

摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

摘要翻译： 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US06743685B1

公开(公告)日：2004-06-01

申请号：US09784629

申请日：2001-02-15

申请人： David D. Wu ,  Michael P. Duane ,  Scott D. Luning

发明人： David D. Wu ,  Michael P. Duane ,  Scott D. Luning

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/26586 ,  H01L21/28202 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66492 ,  H01L29/7833

摘要： A method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the cage region of the doped-poly gate structure adjacent the gate dielectric.

摘要翻译： 提供了一种方法，所述方法包括在衬底的表面上形成栅极电介质，并在栅极电介质上方形成掺杂多晶硅栅极结构，所述掺杂 - 多晶硅结构具有边缘区域。 该方法还包括在与栅极电介质相邻的掺杂多晶硅栅极结构的笼状区域中形成掺杂剂贫化多晶硅区域。

公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US09048136B2

公开(公告)日：2015-06-02

申请号：US13282261

申请日：2011-10-26

申请人： Randy W. Mann ,  Scott D. Luning

发明人： Randy W. Mann ,  Scott D. Luning

IPC分类号： G11C11/00 ,  H01L27/11 ,  H01L27/12 ,  G11C11/412 ,  G11C11/419

CPC分类号： H01L27/1108 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1203

摘要： A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.

摘要翻译： 提供了在衬底上的掩埋氧化物层上的硅层中形成的静态随机存取存储器单元，并且包括第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管形成在掩埋氧化物层下方的第一区域上，其中第一区域具有形成用于下拉晶体管的第一衬底的第一掺杂级。 一对通道晶体管分别耦合到第一和第二反相器的单元节点，并且每一个均形成在掩埋氧化物层下方的第二区域上，其中第二区域具有形成用于通路晶体管的第二衬底的第二掺杂水平。 主动偏置电路在静态随机存取存储器单元的读取，备用和写入操作期间将电位施加到第一和第二后挡板。

公开(公告)号：US20130107610A1

公开(公告)日：2013-05-02

申请号：US13282299

申请日：2011-10-26

申请人： Randy W. Mann ,  Scott D. Luning

发明人： Randy W. Mann ,  Scott D. Luning

IPC分类号： G11C11/34 ,  H01L21/8238 ,  G11C11/00

CPC分类号： H01L27/0207 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/903

摘要： A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.

摘要翻译： 提供了一种静态随机存取存储单元，其包括形成在基板上的第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管驻留在掩埋氧化物层下方的第一区域上，并且具有第一掺杂水平和施加的偏压，为下拉晶体管提供第一电压阈值。 一对通道晶体管耦合第一和第二反相器的单元节点，并且每一个形成在掩埋氧化物层下方的第二区域上，并且具有第二掺杂水平，并且施加的偏置为通路晶体管提供第二电压阈值。 第一电压阈值与提供下拉晶体管和通道晶体管之间的电压阈值控制的第二电压阈值不同。

公开(公告)号：US20130107608A1

公开(公告)日：2013-05-02

申请号：US13282261

申请日：2011-10-26

申请人： Randy W. Mann ,  Scott D. Luning

发明人： Randy W. Mann ,  Scott D. Luning

IPC分类号： G11C11/00 ,  H01L27/12

CPC分类号： H01L27/1108 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1203

摘要： A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.

摘要翻译： 提供了在衬底上的掩埋氧化物层上的硅层中形成的静态随机存取存储器单元，并且包括第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管形成在掩埋氧化物层下方的第一区域上，其中第一区域具有形成用于下拉晶体管的第一衬底的第一掺杂级。 一对通道晶体管分别耦合到第一和第二反相器的单元节点，并且每一个均形成在掩埋氧化物层下方的第二区域上，其中第二区域具有形成用于通路晶体管的第二衬底的第二掺杂水平。 主动偏置电路在静态随机存取存储器单元的读取，备用和写入操作期间将电位施加到第一和第二后挡板。

公开(公告)号：US07087509B1

公开(公告)日：2006-08-08

申请号：US09676197

申请日：2000-09-28

申请人： William R. Roche ,  David Donggang Wu ,  Massud Aminpur ,  Scott D. Luning

发明人： William R. Roche ,  David Donggang Wu ,  Massud Aminpur ,  Scott D. Luning

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28035 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4916

摘要： The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of dopant material in a layer of polysilicon and etching the layer of polysilicon to define a gate electrode having a plurality of sidewalls, each of which have a recess formed therein.

摘要翻译： 本发明涉及一种半导体器件，其具有包括多个侧壁的栅电极，每个侧壁均形成有凹部。 本发明还涉及一种形成半导体器件的方法。 在一个说明性实施例中，该方法包括在多晶硅层中形成掺杂剂材料层并蚀刻多晶硅层以限定具有多个侧壁的栅电极，每个侧壁在其中形成有凹陷。