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    Method of compressing and decompressing a file via cellular automata pre-processing
    33.
    发明授权
    Method of compressing and decompressing a file via cellular automata pre-processing 有权

    公开(公告)号：US11934354B2

    公开(公告)日：2024-03-19

    申请号：US17302374

    申请日：2021-04-30

    Applicant: University of Central Florida Research Foundation, Inc.

    Inventor： Annie S. Wu

    IPC: H03M7/00 ,  G06F16/174 ,  H03M7/30

    CPC classification number: G06F16/1744 ,  H03M7/3059 ,  H03M7/3066 ,  H03M7/6011 ,  H03M7/3086

    Abstract: A method for pre-processing files that can improve file compression rates of existing general-purpose lossless file compression algorithms, particularly for files on which traditional algorithms perform poorly. The elementary cellular automata (CA) pre-processing technique involves finding an optimal CA state that can be used to transform an original file into a format (i.e., an intermediary file) that is more amenable to compression than the original file format. This technique is applicable to multiple file types and may be used to enhance multiple compression algorithms. Evaluation on generated files, as well as samples selected from online text repositories, finds that the CA pre-processing technique improves compression rates by up to 4% and shows promising results for assisting in compressing data that typically induce worst-case behavior in standard compression algorithms.

    Photonic integrated circuit outcoupling array for imaging-based beam steering
    36.
    发明授权
    Photonic integrated circuit outcoupling array for imaging-based beam steering 有权

    公开(公告)号：US11906785B2

    公开(公告)日：2024-02-20

    申请号：US16918792

    申请日：2020-07-01

    Applicant: University of Central Florida Research Foundation, Inc.

    Inventor： Christopher Renshaw ,  Sajad Saghaye Polkoo

    IPC: G02B6/35 ,  G02B6/293

    CPC classification number: G02B6/3596 ,  G02B6/2938 ,  G02B6/3586

    Abstract: A coupler array device may include an array of couplers arranged in a coupler plane, where each of the couplers couples light between the coupler plane and one or more directions outside of the coupler plane. A coupler array device may further include a pixel switch network to selectively couple light into or out of a selected subset of the plurality of couplers, where the pixel switch network may include one or more pixel-network waveguides and pixel-network switches to couple light between couplers and pixel-network waveguides. The coupler array device may further include one or more feed networks including a feed-line waveguide and one or more feed-network switches to couple light between the feed-line waveguide and at least some of the pixel-network waveguides. Light may be routable between selected couplers and selected feed-line waveguides along selected paths by controlling the pixel-network switches and the feed-network switches along the selected paths.

    ACOUSTOELECTRIC AMPLIFICATION IN RESONANT PIEZOELECTRIC-SEMICONDUCTOR CAVITIES
    37.
    发明公开
    ACOUSTOELECTRIC AMPLIFICATION IN RESONANT PIEZOELECTRIC-SEMICONDUCTOR CAVITIES 审中-公开

    公开(公告)号：US20240044843A1

    公开(公告)日：2024-02-08

    申请号：US18490329

    申请日：2023-10-19

    Applicant: University of Central Florida Research Foundation, Inc.

    Inventor： Reza Abdolvand ,  Hakhamanesh Mansoorzare

    IPC: G01N29/04 ,  H10N30/85

    CPC classification number: G01N29/041 ,  H10N30/85 ,  H10N30/87

    Abstract: Interaction of acoustic waves in a piezoelectric-semiconductor resonant cavity with the charge carriers in the semiconductor layer can be directed toward amplification of the acoustic waves; such amplification scheme can be applied in building unilateral amplifiers, zero loss filters, oscillators, high detection range circuit-less wireless sensors, isolators, duplexers, circulators and other acoustic devices. An apparatus for acoustoelectric amplification is described. The apparatus includes a semiconductor layer and a thin piezoelectric layer bonded (or deposited) onto the semiconductor layer forming an acoustic cavity. Two or more tethers forming a current conduction path through the semiconductor layer and two or more access pads to silicon are positioned on two ends of the acoustic cavity and configured to inject a DC current in the semiconductor layer.

    Defect engineering and modification of substrates for supported metal/metal oxide catalysts
    38.
    发明授权
    Defect engineering and modification of substrates for supported metal/metal oxide catalysts 有权

    公开(公告)号：US11890608B2

    公开(公告)日：2024-02-06

    申请号：US17152317

    申请日：2021-01-19

    Applicant: University of Central Florida Research Foundation, Inc.

    Inventor： Fudong Liu ,  Shaohua Xie

    IPC: B01J37/02 ,  B01J23/42 ,  B01J37/16 ,  B01J37/08

    CPC classification number: B01J37/0201 ,  B01J23/42 ,  B01J37/08 ,  B01J37/16

    Abstract: Methods for fabricating thermally stable reducible metal oxide catalyst support structures on a base material using a multi-step incipient wetness impregnation (IWI) process are disclosed. For example, reducible metal oxide catalyst support structures having high surface area and high thermal stability may be formed using a multi-step IWI process, where the support structure is generated through high-temperature calcination between IWI steps. The metal or metal oxide catalysts fabricated using the methods are also disclosed. The generation of engineered surface defects on reducible metal oxides using a gas reduction process to serve as anchoring sites for metal or metal oxide catalysts is also disclosed. Generating engineered defects through a gas reduction process may be a relatively low-cost and scalable process suitable for fabricating efficient catalysts using a wide range of materials.

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