公开(公告)号：US20180232320A1

公开(公告)日：2018-08-16

申请号：US15949940

申请日：2018-04-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Nippon Raval ,  David A. Kaplan ,  Philip Ng

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/455

Abstract: An input-output (IO) memory management unit (IOMMU) uses a reverse map table (RMT) to ensure that address translations acquired from a nested page table are correct and that IO devices are permitted to access pages in a memory when performing memory accesses in a computing device. A translation lookaside buffer (TLB) flushing mechanism is used to invalidate address translation information in TLBs that are affected by changes in the RMT. A modified Address Translation Caching (ATC) mechanism may be used, in which only partial address translation information is provided to IO devices so that the RMT is checked when performing memory accesses for the IO devices using the cached address translation information.

公开(公告)号：US20170277898A1

公开(公告)日：2017-09-28

申请号：US15081126

申请日：2016-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Jeremy W. Powell ,  David A. Kaplan ,  Jesse D. Larrew ,  Thomas R. Woller ,  Joshua Schiffman

IPC: G06F21/60 ,  G06F21/62

CPC classification number: G06F21/602 ,  G06F21/53 ,  G06F21/6209 ,  G06F21/6218

Abstract: A processor employs a security module to manage authentication and encryption keys for the processor. The security module can authenticate itself to other processing systems, such as processing systems providing software to be executed at the processor, can generate keys for encrypting address spaces for the provided software, and can securely import and export information at the encrypted address spaces to and from the processing system. By using a security module that is separate from the processor cores of the processor to perform these security operations, the processing system allows software executing on the processor cores to manage operations based on the authentication and encryption keys without being able to read the keys themselves, thereby preventing unauthorized access by malicious software to the keys.

公开(公告)号：US09311051B2

公开(公告)日：2016-04-12

申请号：US13738899

申请日：2013-01-10

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Kaplan ,  Winthrop J. Wu

IPC: G06F1/02 ,  G06F7/58

CPC classification number: G06F7/588

Abstract: A random number generator may include an input configured to receive a plurality of entropy bits generated by an entropy source of a random number generator, wherein the random number generator is configured to generate a plurality of random numbers; and an entropy health monitor coupled with the input, wherein the entropy health monitor is configured to perform a corrective action based on the plurality of entropy bits.

Abstract translation: 随机数生成器可以包括被配置为接收由随机数发生器的熵源生成的多个熵位的输入，其中所述随机数生成器被配置为生成多个随机数; 以及与所述输入端耦合的熵健康监视器，其中所述熵健康监视器被配置为基于所述多个熵位执行校正动作。

公开(公告)号：US20160085976A1

公开(公告)日：2016-03-24

申请号：US14492786

申请日：2014-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Joshua S. Schiffman ,  David A. Kaplan

IPC: G06F21/62 ,  G06F21/60

CPC classification number: G06F21/62 ,  G06F21/606 ,  G06F21/74 ,  G06F21/83

Abstract: A system and method are disclosed for securely receiving data from an input device coupled to a computing system. The system includes an interface configured to receive data from an input device, a coprocessor, and a host computer, wherein the host computer includes an input handler and a host processor. The host processor is configured to execute code in a normal mode and in a privileged mode. The host processor switches from the normal mode to the secure mode upon data being available from the interface while the host computer is in a secure input mode. The input handler receives the data from the interface and sends the received data to the coprocessor responsive to receiving the data while operating in the secure mode.

Abstract translation: 公开了用于从耦合到计算系统的输入设备安全地接收数据的系统和方法。 该系统包括被配置为从输入设备，协处理器和主计算机接收数据的接口，其中主机包括输入处理器和主机处理器。 主机处理器被配置为以正常模式和特权模式执行代码。 当主机处于安全输入模式时，主机处理器可以从接口获得数据，从正常模式切换到安全模式。 输入处理器接收来自接口的数据，并且响应于在安全模式下操作时接收数据而将接收到的数据发送到协处理器。

公开(公告)号：US20140317357A1

公开(公告)日：2014-10-23

申请号：US13864844

申请日：2013-04-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. Kaplan ,  Tarun Nakra

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0862

Abstract: A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel.

Abstract translation: 处理器包括高速缓存存储器，包括指令执行单元的第一核心以及将高速缓冲存储器耦合到第一核心的存储器总线。 存储器总线可操作以接收用于高速缓冲存储器的数据的高速缓存行的第一部分，第一核可操作以识别针对高速缓存行和第一部分的多个数据请求，并选择所识别的多个数据之一 请求执行，并且存储器总线可操作以并行地将第一部分转发到指令执行单元和高速缓冲存储器。

公开(公告)号：US20140164789A1

公开(公告)日：2014-06-12

申请号：US13708782

申请日：2012-12-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. Kaplan

IPC: G06F21/44

CPC classification number: G06F21/572

Abstract: A single or multicore processor having a separate hardware cryptographic engine (HCE) for microcode patch updates is presented. Microcode in each core is modified to utilize the HCE for patch updates. Various arrangements are presented. Memory for HCE processing can include shared L2 or L3 memory or a separate DRAM configured in the address space of each core or set of cores and the HCE. In some embodiments, the HCE may be located on a circuit card attached to an extension bus, such as a PCIe or LPC bus.

Abstract translation: 提出了具有用于微代码补丁更新的单独的硬件加密引擎（HCE）的单核或多核处理器。 修改每个核心中的微代码以利用HCE进行补丁更新。 介绍各种安排。 用于HCE处理的存储器可以包括共享的L2或L3存储器或在每个核心或一组核心和HCE的地址空间中配置的单独的DRAM。 在一些实施例中，HCE可以位于连接到扩展总线（例如PCIe或LPC总线）的电路卡上。

公开(公告)号：US20140129794A1

公开(公告)日：2014-05-08

申请号：US13672188

申请日：2012-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Kaplan ,  Stephen P. Thompson

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/10 ,  G06F12/1009

Abstract: A method includes performing a speculative tablewalk. The method includes performing a tablewalk to determine an address translation for a speculative operation and determining whether the speculative operation has been upgraded to a non-speculative operation concurrently with performing the tablewalk. An apparatus is provided that includes a load-store unit to maintain execution operations. The load-store unit includes a tablewalker to perform a tablewalk and includes an input indicative of the operation being speculative or non-speculative as well as a state machine to determine actions performed during the tablewalk based on the input. The apparatus also includes a translation look-aside buffer. Computer readable storage devices for performing the methods and adapting a fabrication facility to manufacture the apparatus are provided.

Abstract translation: 一种方法包括执行推测性行进。 该方法包括执行行进台以确定用于投机操作的地址转换，并且确定投机操作是否已经与执行台式机同时升级到非投机操作。 提供一种装置，其包括用于维持执行操作的加载存储单元。 加载存储单元包括执行台面的行进者，并且包括指示操作是投机或不推测的输入以及基于输入来确定在行进过程中执行的动作的状态机。 该装置还包括翻译后备缓冲器。 提供了用于执行方法和适配制造设备以制造该装置的计算机可读存储装置。