公开(公告)号：US5527726A

公开(公告)日：1996-06-18

申请号：US425269

申请日：1995-04-17

申请人： George E. Possin ,  Robert F. Kwasnick

发明人： George E. Possin ,  Robert F. Kwasnick

IPC分类号： H01L29/78 ,  H01L21/027 ,  H01L21/336 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/66765 ,  H01L21/0274 ,  Y10S148/10 ,  Y10S148/102 ,  Y10S148/105

摘要： A thin-film field-effect transistor is fabricated by forming an electrically insulative island between the source and the drain. A cap is formed on the island with a brim that overhangs the island. A layer of source-drain metal, which will subsequently constitute the source and drain contacts, is then deposited upon the source, the drain, and the cap, but the overhang creates an exposed region which can be attacked by an etchant. When the etchant is applied, it etches away the cap, thereby lifting off the source-drain metal which coated the cap, leaving the fully formed source and drain contacts separated by the island.

摘要翻译： 通过在源极和漏极之间形成电绝缘岛来制造薄膜场效应晶体管。 在岛上形成一个帽子，一个悬垂在岛上的边缘。 随后将构成源极和漏极触点的源极 - 漏极金属层沉积在源极，漏极和帽上，但是突出部产生可被腐蚀剂侵蚀的暴露区域。 当施加蚀刻剂时，其蚀刻掉盖，从而提起涂覆盖的源极 - 漏极金属，留下由岛隔开的完全形成的源极和漏极接触。

公开(公告)号：US5384271A

公开(公告)日：1995-01-24

申请号：US130807

申请日：1993-10-04

申请人： Robert F. Kwasnick ,  George E. Possin

发明人： Robert F. Kwasnick ,  George E. Possin

IPC分类号： H01L21/324 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L21/24

CPC分类号： H01L29/66765 ,  Y10S438/958

摘要： A method of fabricating a thin film transistor having reduced off-current leakage includes the steps of forming a TFT body with a channel region disposed between a source electrode and a drain electrode and then passivating the exposed portion of the channel region. The passivation includes the steps of wet etching the exposed portions of the channel region in an hydrofluoric acid etchant for a first selected etch time; dry etching the exposed channel region in a reactive ion etching procedure for a second selected etch time; wet etching the channel region again with hydrofluoric acid for a third selected etch time; and then treating the channel region with a cleansing agent, such as photoresist stripper; and annealing the exposed portion of the channel region.

摘要翻译： 制造具有减少的截止电流泄漏的薄膜晶体管的方法包括以下步骤：形成具有设置在源极和漏极之间的沟道区，然后钝化沟道区的暴露部分的TFT体。 钝化包括在第一选择的蚀刻时间内在氢氟酸蚀刻剂中湿蚀刻沟道区的暴露部分的步骤; 在反应离子蚀刻过程中对第二选择的蚀刻时间的暴露的沟道区进行干蚀刻; 用氢氟酸再次湿蚀刻通道区域进行第三选择的蚀刻时间; 然后用清洁剂如光致抗蚀剂剥离剂处理通道区域; 以及对通道区域的暴露部分进行退火。

公开(公告)号：US5362660A

公开(公告)日：1994-11-08

申请号：US977967

申请日：1992-11-18

申请人： Robert F. Kwasnick ,  George E. Possin ,  David E. Holden ,  Richard J. Saia

发明人： Robert F. Kwasnick ,  George E. Possin ,  David E. Holden ,  Richard J. Saia

IPC分类号： H01L21/3213 ,  H01L21/336 ,  H01L29/45 ,  H01L21/265

CPC分类号： H01L29/66765 ,  H01L21/32139 ,  H01L29/458 ,  Y10S438/97

摘要： Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.

摘要翻译： 通过采用具有第一相对薄的第一导体层和第二相对较厚的第二导体层的源极/漏极金属化，薄膜晶体管中的最小线间距减小，并且线间隔均匀性增加。 第二导体被选择为可以在第一导体存在的情况下优先蚀刻的导体，由此第一导体充当用于图案化源极/漏极金属化的第二导体部分的蚀刻剂的蚀刻停止。 该蚀刻优选使用干蚀刻进行。 干蚀刻通常比湿式蚀刻提供对线宽度的更好的控制。 第二导体的蚀刻可以通过干法蚀刻工艺进行，该蚀刻工艺以基本上与第二导体相同的速率蚀刻光致抗蚀剂，由此第二导体设置有大致为45°的侧壁斜率，这提高了后续提供的钝化质量 共形钝化层的沉积。

公开(公告)号：US5340758A

公开(公告)日：1994-08-23

申请号：US938562

申请日：1992-08-28

申请人： Ching-Yeu Wei ,  George E. Possin ,  Robert F. Kwasnick

发明人： Ching-Yeu Wei ,  George E. Possin ,  Robert F. Kwasnick

IPC分类号： H01L29/40 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L21/28008 ,  H01L29/42384 ,  H01L29/78669

摘要： A self-aligned, inverted, thin film field effect transistor is produced by patterning the gate electrode to have tapered edges followed by conformal deposition of subsequent layers of the device structure up through a support layer followed by deposition of a subordinate layer such as the source/drain metallization) on the support layer. The subordinate layer itself may be a planarization or non-conformal layer or may have a subsequent non-conformal planarization layer disposed thereon. Thereafter, the structure is non-selectively etched (preferably reactive ion etched) until the support layer is exposed by the creation of an aperture in the subordinate layer in alignment with raised portions of the reference layer while leaving the subordinate layer present on other parts of the structure. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the gate conductor using a selective etch method.

摘要翻译： 通过对栅电极进行图案化以产生渐缩边缘，随后将器件结构的后续层向上保持沉积通过支撑层，随后沉积下层（例如源极）而产生自对准反转的薄膜场效应晶体管 /漏极金属化）。 下层本身可以是平面化或非保形层，或者可以具有设置在其上的随后的非保形平面化层。 此后，结构被非选择性蚀刻（优选为反应离子蚀刻），直到支撑层通过在下位层中形成与参考层的凸起部分对准的孔而暴露，同时使下层存在于其它部分 结构。 此后，使用选择性蚀刻方法，使源极和漏极相对于栅极导体自对准制造器件的其余部分。

公开(公告)号：US5293417A

公开(公告)日：1994-03-08

申请号：US30909

申请日：1993-03-15

申请人： Ching-Yeu Wei ,  Robert F. Kwasnick ,  George E. Possin

发明人： Ching-Yeu Wei ,  Robert F. Kwasnick ,  George E. Possin

IPC分类号： G21K1/02

CPC分类号： G21K1/025

摘要： A collimator for use in an imaging system with a radiation point source is formed from a plurality of collimator plates stacked together. Passages in each collimator plate in conjunction with the respective passages in adjoining plates form a plurality of channels through the collimator. The channel longitudinal axes are aligned with selected orientation angles that correspond to the direct beam path from the radiation source to the radiation detectors. The collimator plates are made up of patterned sheets of radiation absorbent material or alternatively comprise patterned photosensitive material substrates coated with a radiation absorbent material. The cross-sectional shape of each channel corresponds to the cross-sectional shape of the radiation detecting area of the detector element adjoining the channel. A method of forming a collimator includes the steps of selectively removing material from the collimator plates to form the passages therein, and stacking the patterned collimator plates together to align them so that the respective adjacent passages form a channel aligned with respective selected orientation angles corresponding to direct paths of radiation from the radiation source to the detector elements in the assembled array.

摘要翻译： 用于具有辐射点源的成像系统中的准直器由堆叠在一起的多个准直器板形成。 每个准直板中的通道与相邻板中的相应通道结合形成通过准直器的多个通道。 通道纵向轴线对应于对应于从辐射源到辐射探测器的直接光束路径的选定取向角度。 准直板由图案化的辐射吸收材料片构成，或者包括涂覆有辐射吸收材料的图案化感光材料基底。 每个通道的横截面形状对应于邻近通道的检测器元件的辐射检测区域的横截面形状。 一种形成准直器的方法包括以下步骤：选择性地从准直板移除材料以在其中形成通道，并且将图案化的准直器板堆叠在一起以对准它们，使得相应的相邻通道形成与各自选定的取向角对应的通道 从辐射源到组装阵列中的检测器元件的直接辐射路径。

公开(公告)号：US5281546A

公开(公告)日：1994-01-25

申请号：US939749

申请日：1992-09-02

申请人： George E. Possin ,  Robert F. Kwasnick ,  Brian W. Giambattista

发明人： George E. Possin ,  Robert F. Kwasnick ,  Brian W. Giambattista

IPC分类号： H01L21/30 ,  H01L21/336 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/66765 ,  H01L21/3003 ,  H01L29/78669 ,  Y10S438/909 ,  Y10S438/91

摘要： A method of fabricating a thin film transistor (TFT) including the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer over the gate conductor; depositing a layer of amorphous silicon over the gate dielectric layer; treating the exposed surface of the amorphous silicon with a hydrogen plasma; depositing a layer of n+ doped silicon over the treated amorphous silicon surface such that an interface is formed between the amorphous silicon and the n+ doped layer that has relatively low contact resistance; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The TFT material layers are preferably deposited by plasma enhanced chemical vapor deposition. The hydrogen plasma treatment is advantageously used both when vacuum is maintained during the various deposition steps, and when vacuum is broken, for the purposes of patterning the amorphous silicon layer or the like, such that the amorphous silicon layer is passivated with the hydrogen plasma treatment prior to the deposition of the n+ doped layer.

摘要翻译： 一种制造薄膜晶体管（TFT）的方法，包括在基板上形成栅极导体的步骤; 在所述栅极导体上沉积栅极电介质层; 在所述栅极电介质层上沉积非晶硅层; 用氢等离子体处理非晶硅的暴露表面; 在经处理​​的非晶硅表面上沉积n +掺杂的硅层，使得在具有相对低的接触电阻的非晶硅和n +掺杂层之间形成界面; 在n +掺杂层上沉积一层源极/漏极金属化层; 以及图案化源极/漏极金属化层和下层n +掺杂层的部分以形成源极和漏极。 优选通过等离子体增强化学气相沉积来沉积TFT材料层。 有利地，当在各种沉积步骤期间保持真空并且当真空破裂时，为了图案化非晶硅层等的目的，有利地使用氢等离子体处理，使得非晶硅层被氢等离子体处理钝化 在沉积n +掺杂层之前。

公开(公告)号：US4778258A

公开(公告)日：1988-10-18

申请号：US104452

申请日：1987-10-05

申请人： Harold G. Parks ,  William W. Piper ,  George E. Possin

发明人： Harold G. Parks ,  William W. Piper ,  George E. Possin

IPC分类号： G02F1/1368 ,  H01L27/12 ,  G02F1/13

CPC分类号： H01L27/12 ,  G02F1/1368 ,  Y10S359/90

摘要： A process for the fabrication of thin film field effect transistors in active matrix liquid crystal display devices includes the utilization of a protective, conductive tab disposed on a corner portion of the pixel electrodes. Electrical contact is made to the pixel electrodes not directly, but rather through a via opening in protective, insulative and amorphous silicon layers. The structure is particularly advantageous in that it permits the utilization of a wider range of gate and upper level metallization materials, particularly aluminum, whose etchants are otherwise found deleterious to pixel electrode material such as indium tin oxide. The structure of the present invention is seen to be readily fabricatable in accordance with high yield fabrication procedures.

摘要翻译： 在有源矩阵液晶显示装置中制造薄膜场效应晶体管的方法包括利用设置在像素电极的角部上的保护导电片。 不直接地对像素电极进行电接触，而是通过保护性，绝缘和非晶硅层中的通孔开口进行电接触。 该结构是特别有利的，因为其允许利用较宽范围的栅极和上层金属化材料，特别是铝，其蚀刻剂被认为对诸如氧化铟锡的像素电极材料有害。 本发明的结构被认为可以根据高产量制造方法容易地制造。

公开(公告)号：US4774207A

公开(公告)日：1988-09-27

申请号：US39854

申请日：1987-04-20

申请人： George E. Possin

发明人： George E. Possin

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L21/336 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L21/28512 ,  Y10S438/974

摘要： Electrical contact to doped amorphous silicon material is enhanced by depositing a thin layer of molybdenum on the amorphous silicon surface and subsequently removing it. This treatment is found to permanently alter the silicon surface so as to facilitate and improve electrical contact to the silicon material by subsequently deposited metallization layers for source and drain electrode attachment. The layer of molybdenum which is deposited and removed need only be approximately 50 nanometers in thickness to produce desirable results. The method is particularly useful in the fabrication of thin film, inverted, amorphous silicon field effect transistors. Furthermore, such devices are particularly useful in the fabrication of liquid crystal display systems employing such field effect transistors in matrix addressed arrays used for switching individually selected pixel elements.

摘要翻译： 通过在非晶硅表面上沉积钼薄层并随后将其去除而增强与掺杂非晶硅材料的电接触。 发现这种处理永久地改变了硅表面，以便通过随后沉积的用于源电极和漏电极附着的金属化层促进和改善与硅材料的电接触。 沉积和去除的钼层仅需要约50纳米的厚度以产生期望的结果。 该方法在薄膜反转的非晶硅场效应晶体管的制造中特别有用。 此外，这样的器件在制造使用用于切换单独选择的像素元件的矩阵寻址阵列中的这种场效应晶体管的液晶显示系统中是特别有用的。

公开(公告)号：US4534016A

公开(公告)日：1985-08-06

申请号：US512070

申请日：1983-07-08

申请人： Conilee G. Kirkpatrick ,  Michael S. Adler ,  George E. Possin

发明人： Conilee G. Kirkpatrick ,  Michael S. Adler ,  George E. Possin

IPC分类号： G11B9/10 ,  G11C11/42

CPC分类号： G11B9/10

摘要： A beam-addressed memory system for digital memory recording and reading which comprises an electron beam generating and focusing subsystem, an electron detecting subsystem, electronic control and interface circuit means, and a storage medium consisting essentially of a cross-linkable polymeric film having an implanted surface layer of heavy metal ions.

摘要翻译： 一种用于数字存储器记录和读取的光束寻址存储器系统，其包括电子束产生和聚焦子系统，电子检测子系统，电子控制和接口电路装置，以及基本上由可交联聚合物膜组成的存储介质，该可交联聚合物膜具有植入 表层重金属离子。

公开(公告)号：US08409908B2

公开(公告)日：2013-04-02

申请号：US12512714

申请日：2009-07-30

申请人： Wen Li ,  Jonathan D. Short ,  George E. Possin

发明人： Wen Li ,  Jonathan D. Short ,  George E. Possin

IPC分类号： H01L21/00

CPC分类号： H01L27/14601 ,  A61B6/032 ,  G01T1/2018 ,  G01T1/249 ,  H01L31/105

摘要： An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer.

摘要翻译： 减少光电二极管热增益系数的装置包括具有光照射侧的体半导体材料。 体半导体材料包括少数电荷载流子扩散长度特性，其被配置为基本上匹配预定的空穴扩散长度值和被配置为基本匹配预定的光电二极管层厚度的厚度。 该装置还包括耦合到体半导体材料的光照射侧的死层，该死层具有被配置为基本匹配预定厚度值的厚度，并且其中由少数载体产生的增益热系数的绝对值 体半导体材料的扩散长度特性被配置为基本上匹配由于死层的厚度而导致的增益热系数的绝对值。