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    Flexible dictionary sharing for compressed caches
    31.
    发明授权
    Flexible dictionary sharing for compressed caches 有权

    公开(公告)号：US12135653B2

    公开(公告)日：2024-11-05

    申请号：US18158212

    申请日：2023-01-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander D. Breslow ,  John Kalamatianos

    IPC: G06F12/0895 ,  H03M7/30

    Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.

    ACCELERATING RELAXED REMOTE ATOMICS ON MULTIPLE WRITER OPERATIONS
    32.
    发明公开
    ACCELERATING RELAXED REMOTE ATOMICS ON MULTIPLE WRITER OPERATIONS 审中-公开

    公开(公告)号：US20240211134A1

    公开(公告)日：2024-06-27

    申请号：US18087964

    申请日：2022-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Karthik Ramu Sangaiah ,  Anthony Thomas Gutierrez

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.

    SPECULATIVE DRAM REQUEST ENABLING AND DISABLING
    34.
    发明公开
    SPECULATIVE DRAM REQUEST ENABLING AND DISABLING 审中-公开

    公开(公告)号：US20240111420A1

    公开(公告)日：2024-04-04

    申请号：US17956417

    申请日：2022-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jagadish B. Kotra ,  John Kalamatianos

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0673

    Abstract: Methods, devices, and systems for retrieving information based on cache miss prediction. It is predicted, based on a history of cache misses at a private cache, that a cache lookup for the information will miss a shared victim cache. A speculative memory request is enabled based on the prediction that the cache lookup for the information will miss the shared victim cache. The information is fetched based on the enabled speculative memory request.

    VLIW Dynamic Communication
    36.
    发明公开
    VLIW Dynamic Communication 审中-公开

    公开(公告)号：US20230409336A1

    公开(公告)日：2023-12-21

    申请号：US17843640

    申请日：2022-06-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sriseshan Srikanth ,  Karthik Ramu Sangaiah ,  Anthony Thomas Gutierrez ,  Vedula Venkata Srikant Bharadwaj ,  John Kalamatianos

    IPC: G06F9/38 ,  G06F9/32

    CPC classification number: G06F9/3853 ,  G06F9/3885 ,  G06F9/321

    Abstract: In accordance with described techniques for VLIW Dynamic Communication, an instruction that causes dynamic communication of data to at least one processing element of a very long instruction word (VLIW) machine is dispatched to a plurality of processing elements of the VLIW machine. A first count of data communications issued by the plurality of processing elements and a second count of data communications served by the plurality of processing elements are maintained. At least one additional instruction is determined for dispatch to the plurality of processing elements of the VLIW machine based on the first count and the second count. For example, an instruction that is independent of the instruction is determined for dispatch while the first count and the second count are unequal, and an instruction that is dependent on the instruction is determined for dispatch based on the first count and the second count being equal.

    APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS AND NON-NEAR-MEMORY PROCESSING COMMANDS IN A MEMORY CONTROLLER
    38.
    发明公开
    APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS AND NON-NEAR-MEMORY PROCESSING COMMANDS IN A MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20230205706A1

    公开(公告)日：2023-06-29

    申请号：US17561454

    申请日：2021-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Niti Madan ,  John Kalamatianos

    IPC: G06F12/1009 ,  G06F12/0882 ,  G06F12/02

    CPC classification number: G06F12/1009 ,  G06F12/0882 ,  G06F12/0207

    Abstract: An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. The memory controller maintains and uses a page table to properly configure memory elements, such as banks in a memory module, for the next memory command, whether a PIM command or a non-PIM command. The page table tracks the status of memory elements as of the most recent memory command that was issued. The page table includes an “All Bank” entry that indicates the status of banks after processing the most recent PIM command. For example, the All Banks entry indicates whether all the banks have a row open and if so, specifies the open row for all the banks.

    Controlling accesses to a branch prediction unit for sequences of fetch groups
    39.
    发明授权
    Controlling accesses to a branch prediction unit for sequences of fetch groups 有权

    公开(公告)号：US11513801B2

    公开(公告)日：2022-11-29

    申请号：US16127093

    申请日：2018-09-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Adithya Yalavarti ,  John Kalamatianos ,  Matthew R. Poremba

    IPC: G06F9/38 ,  G06F1/3287 ,  G06F9/30

    Abstract: An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.

    Masked fault detection for reliable low voltage cache operation
    40.
    发明授权
    Masked fault detection for reliable low voltage cache operation 有权

    公开(公告)号：US11509333B2

    公开(公告)日：2022-11-22

    申请号：US17125145

    申请日：2020-12-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Shrikanth Ganapathy ,  John Kalamatianos

    IPC: G11C29/00 ,  H03M13/35 ,  G06F12/0895 ,  G06F11/10

    Abstract: Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

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