公开(公告)号：US11880926B2

公开(公告)日：2024-01-23

申请号：US17745410

申请日：2022-05-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.

公开(公告)号：US20240004562A1

公开(公告)日：2024-01-04

申请号：US17854903

申请日：2022-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Mark Fowler ,  Anthony Asaro ,  Vydhyanathan Kalyanasundharam

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0679 ,  G06F3/0604

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

公开(公告)号：US20230055695A1

公开(公告)日：2023-02-23

申请号：US18045128

申请日：2022-10-07

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F12/1009 ,  G06F12/14 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US20220269620A1

公开(公告)日：2022-08-25

申请号：US17666974

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI Technologies ULC

Inventor： Benjamin T. SANDER ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Michael Mantor

IPC: G06F12/1027 ,  G06F12/0893

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

公开(公告)号：US11335052B2

公开(公告)日：2022-05-17

申请号：US16179376

申请日：2018-11-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.

公开(公告)号：US10991146B2

公开(公告)日：2021-04-27

申请号：US16723232

申请日：2019-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. Kazakov ,  Mark Fowler

IPC: G06T15/04 ,  G06T15/00

Abstract: A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps that indicate texels that are resident in the PRT resource. The processor translates the normalized coordinates to texel coordinates in the one or more residency maps based on the offset and accesses, in response to the request, the one or more residency maps based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.

公开(公告)号：US20210011760A1

公开(公告)日：2021-01-14

申请号：US16938381

申请日：2020-07-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F12/1009 ,  G06F12/14 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US10474468B2

公开(公告)日：2019-11-12

申请号：US15439540

申请日：2017-02-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Mantor ,  Brian D. Emberling ,  Mark Fowler ,  Mark M. Leather

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for processing variable wavefront sizes on a processor are disclosed. In one embodiment, a processor includes at least a scheduler, cache, and multiple execution units. When operating in a first mode, the processor executes the same instruction on multiple portions of a wavefront before proceeding to the next instruction of the shader program. When operating in a second mode, the processor executes a set of instructions on a first portion of a wavefront. In the second mode, when the processor finishes executing the set of instructions on the first portion of the wavefront, the processor executes the set of instructions on a second portion of the wavefront, and so on until all portions of the wavefront have been processed. The processor determines the operating mode based on one or more conditions.

公开(公告)号：US10152434B2

公开(公告)日：2018-12-11

申请号：US15385566

申请日：2016-12-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Rostyslav Kyrychynskyi ,  Anthony Asaro ,  Kostantinos Danny Christidis ,  Mark Fowler ,  Michael J. Mantor ,  Robert Scott Hartog

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40

Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.

公开(公告)号：US09934551B2

公开(公告)日：2018-04-03

申请号：US15282336

申请日：2016-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark Fowler

IPC: G09G5/00 ,  G06T1/60 ,  G06T11/40 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T11/40 ,  G06T2200/12 ,  G06T2200/28

Abstract: Embodiments of the present invention are directed to improving the performance of anti-aliased image rendering. One embodiment is a method of rendering a pixel from an anti-aliased image. The method includes: storing a first set and a second set of samples from a plurality of anti-aliased samples of the pixel respectively in a first memory and a second memory; and rendering a determined number of said samples from one of only the first set or the first and second sets. Corresponding system and computer program product embodiments are also disclosed.