公开(公告)号：US08076703B2

公开(公告)日：2011-12-13

申请号：US12603353

申请日：2009-10-21

Applicant: Akif Sultan ,  James F. Buller ,  Kaveri Mathur

Inventor： Akif Sultan ,  James F. Buller ,  Kaveri Mathur

IPC: H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

Abstract translation: 提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

公开(公告)号：US07504270B2

公开(公告)日：2009-03-17

申请号：US11425913

申请日：2006-06-22

Applicant: David D. Wu ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

Inventor： David D. Wu ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

IPC: G10R31/26 ,  H01L21/66

CPC classification number: H01L22/34 ,  G03F7/70658 ,  H01L22/12

Abstract: The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

Abstract translation: 本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构 表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果 以确定制造性角落四舍五入对多个测试结构的性能的影响。

公开(公告)号：US07176095B1

公开(公告)日：2007-02-13

申请号：US10790939

申请日：2004-03-01

Applicant: Akif Sultan ,  David Wu ,  Wen-Jie Qi ,  Mark Fuselier

Inventor： Akif Sultan ,  David Wu ,  Wen-Jie Qi ,  Mark Fuselier

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of fabricating halo regions are provided. In one aspect, a method is provided of fabricating a first halo region and a second halo region for a circuit device of a first conductivity type and having a gate structure with first and second sidewalls. The first halo region of a second conductivity type is formed by implanting the substrate with impurities in a first direction toward the first sidewall of the gate structure. The second halo region of the second conductivity type is formed by implanting the substrate with impurities in a second direction toward the second sidewall of the gate structure. The first and second halo regions are formed without implanting impurities in a direction substantially perpendicular to the first and second directions.

Abstract translation: 提供制造晕圈的方法。 在一个方面，提供了一种制造用于第一导电类型的电路器件的第一卤素区域和第二卤素区域的方法，并具有具有第一和第二侧壁的栅极结构。 第二导电类型的第一晕区是通过沿着第一方向将杂质注入栅极结构的第一侧壁而形成的。 第二导电类型的第二晕区是通过向栅极结构的第二侧壁向第二方向注入具有杂质的衬底形成的。 形成第一和第二晕圈，而不在基本上垂直于第一和第二方向的方向上植入杂质。

公开(公告)号：US20070026599A1

公开(公告)日：2007-02-01

申请号：US11191684

申请日：2005-07-27

Applicant: Igor Peidous ,  Akif Sultan ,  Mario Pelella

Inventor： Igor Peidous ,  Akif Sultan ,  Mario Pelella

IPC: H01L21/8238 ,  H01L29/94

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: Methods are provided for fabricating a stressed MOS device. The method comprises the steps of forming a plurality of parallel MOS transistors in and on a semiconductor substrate. The parallel MOS transistors having a common source region, a common drain region, and a common gate electrode. A first trench is etched into the substrate in the common source region and a second trench is etched into the substrate in the common drain region. A stress inducing semiconductor material that has a crystal lattice mismatched with the semiconductor substrate is selectively grown in the first and second trenches. The growth of the stress inducing material creates both compressive longitudinal and tensile transverse stresses in the MOS device channel that enhance the drive current of P-channel MOS transistors. The decrease in drive current of N-channel MOS transistors caused by the compressive stress component is offset by the tensile stress component.

Abstract translation: 提供了制造应力MOS器件的方法。 该方法包括在半导体衬底中和半导体衬底上形成多个并联MOS晶体管的步骤。 并联MOS晶体管具有公共源极区，公共漏极区和公共栅电极。 第一沟槽被蚀刻到公共源极区域中的衬底中，并且第二沟槽被蚀刻到公共漏极区域中的衬底中。 在第一和第二沟槽中选择性地生长具有与半导体衬底失配的晶格的应力诱导半导体材料。 应力诱导材料的生长在MOS器件通道中产生压缩纵向和拉伸横向应力，从而增强P沟道MOS晶体管的驱动电流。 由压缩应力分量引起的N沟道MOS晶体管的驱动电流的减小由拉应力分量抵消。

公开(公告)号：US06864516B2

公开(公告)日：2005-03-08

申请号：US10085903

申请日：2002-02-28

Applicant: Andy Wei ,  Akif Sultan ,  David Wu

Inventor： Andy Wei ,  Akif Sultan ,  David Wu

IPC: H01L21/265 ,  H01L21/322 ,  H01L21/336 ,  H01L29/786 ,  H01L29/74

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26593 ,  H01L21/3221 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: Various circuit devices incorporating junction-traversing dislocation regions and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region in a device region of a semiconductor-on-insulator substrate. The impurity region defines a junction. A dislocation region is formed in the device region that traverses the junction. The dislocation region provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract translation: 提供了结合穿越位错区域的各种电路装置及其制造方法。 一方面，提供了一种处理方法，其包括在绝缘体上半导体衬底的器件区域中形成杂质区域。 杂质区限定了一个结。 在穿过结的器件区域中形成位错区域。 位错区域提供了中和装置的浮体中滞留电荷的途径。

公开(公告)号：US6087209A

公开(公告)日：2000-07-11

申请号：US126775

申请日：1998-07-31

Applicant: Geoffrey Choh-Fei Yeap ,  Akif Sultan ,  Shekhar Pramanick

Inventor： Geoffrey Choh-Fei Yeap ,  Akif Sultan ,  Shekhar Pramanick

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1079 ,  Y10S148/053

Abstract: Ultra shallow, low resistance LDD junctions are achieved by forming an LDD implant generating an interstitial-rich section and forming a sub-surface, non-amorphous region generating a vacancy-rich region substantially overlapping the interstitial rich region generated when forming the LDD implant. Embodiments include ion implanting, Ge or Si to form surface amorphous and sub-surface, non-amorphous regions, and implanting B or BF.sub.2 to form the impurity region. Embodiments include forming the sub-surface, non-amorphous region before or after generating the surface amorphous region, and forming the impurity region before or after forming the sub-surface, non-amorphous region but after forming the surface amorphous region.

Abstract translation: 通过形成LDD注入产生富含间隙的部分并形成基本上与形成LDD植入物时产生的间隙富集区域重叠的空位丰富区域的亚表面非非晶区域来实现超浅，低电阻LDD结。 实施例包括离子注入，Ge或Si以形成表面无定形和亚表面非非晶区域，以及注入B或BF 2以形成杂质区域。 实施例包括在产生表面无定形区域之前或之后形成子表面非非晶区域，以及在形成子表面非非晶区域之后或在形成表面无定形区域之后形成杂质区域。

公开(公告)号：US06008099A

公开(公告)日：1999-12-28

申请号：US50689

申请日：1998-03-30

Applicant: Akif Sultan ,  Dong-Hyuk Ju

Inventor： Akif Sultan ,  Dong-Hyuk Ju

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586

Abstract: A method of making a lightly doped drain transistor includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and forming a drain (70) in a drain region (58) and a source (72) in a source region (60) of the substrate (56). The method further includes generating interstitials (62) near a lateral edge of at least one of the drain (70) and the source (72) and thermally treating the substrate (56). The thermal treatment cause the interstitials (62) to enhance a lateral diffusion (84) of the drain (70) under the gate oxide (54) without substantially impacting a vertical diffusion (82) of the drain (70) or the source (72). The enhanced lateral diffusion (84) results in the formation of at least one of a lightly doped drain extension region (75) and a lightly doped source extension region (76) without an increase in a junction depth of the drain (70) or the source (72). The step of generating interstitials (62) may include the step of implanting at least one of the drain region (58) and the source region (60) of the substrate (56) with a large tilt angle implant which creates the interstitials (62) at a location near the gate oxide (54).

Abstract translation: 一种制造轻掺杂漏极晶体管的方法包括以下步骤：在半导体衬底（56）上形成栅电极（52）和栅极氧化物（54），并在漏区（58）中形成漏极（70） 源极（72）在衬底（56）的源极区（60）中。 所述方法还包括在所述排水口（70）和所述源（72）中的至少一个的侧边缘附近产生间隙（62）并热处理所述衬底（56）。 热处理使间隙（62）增强栅极氧化物（54）下面的漏极（70）的横向扩散（84），而基本上不影响漏极（70）或源极（72）的垂直扩散（82） ）。 增强的横向扩散（84）导致轻掺杂漏极延伸区域（75）和轻掺杂源极延伸区域（76）中的至少一个的形成，而不会增加漏极（70）或 来源（72）。 产生间隙（62）的步骤可以包括用产生间隙（62）的大倾斜角植入物植入衬底（56）的漏区（58）和源区（60）中的至少一个的步骤， 在栅极氧化物（54）附近。