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151 条记录 (耗时 0.023 秒)

    Array of sidewall-contacted antifuses having diffused bit lines
    31.
    发明授权
    Array of sidewall-contacted antifuses having diffused bit lines 有权
    具有扩散位线的侧壁接触反熔丝阵列

    公开(公告)号：US06180994B2

    公开(公告)日：2001-01-30

    申请号：US09234007

    申请日：1999-01-19

    申请人： Albert Bergemont ,  Alexander Kalnitsky

    发明人： Albert Bergemont ,  Alexander Kalnitsky

    IPC分类号： H01L2900

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An array of sidewall-contacted antifuses is formed by a method that reduces the sensitivity of the array to masking alignment errors. The array includes a plurality of spaced-apart bit lines which are formed in a semiconductor material. Rows and columns of insulated contacts are formed on the semiconductor material such that each bit line is contacted a plurality of times by an insulated contact. In each row of contacts, each contact has an exposed sidewall. A plurality of word lines are formed over the contacts such that a word line is formed over each exposed sidewall in a row of exposed sidewalls. The word line includes a dielectric layer and a conductive layer.

    摘要翻译： 通过一种降低阵列对屏蔽对准误差的灵敏度的方法形成侧壁接触的反熔丝阵列。 阵列包括形成在半导体材料中的多个间隔开的位线。 绝缘触点的行和列形成在半导体材料上，使得每个位线通过绝缘接触多次接触。 在每排触点中，每个触点具有暴露的侧壁。 在触点上形成多个字线，使得在一排暴露的侧壁中的每个暴露的侧壁上形成字线。 字线包括电介质层和导电层。

    Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data
    33.
    发明授权
    Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data 有权
    可擦除的rubhmann-bentchkowsky存储晶体管存储多个数据位

    公开(公告)号：US6157574A

    公开(公告)日：2000-12-05

    申请号：US394299

    申请日：1999-09-10

    申请人： Alexander Kalnitsky ,  Albert Bergemont

    发明人： Alexander Kalnitsky ,  Albert Bergemont

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115 ,  H01L29/788

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/7887 ,  G11C2216/10 ,  G11C7/06

    摘要： Multiple bits of data are stored in an erasable Frohmann-Bentchkowsky p-channel memory transistor which has a plurality of upper plates that are switchably connectable to an erase voltage. The multiple bits of data define a number of logic states which, in turn, define a number of corresponding charge ranges on the floating gate. The charge ranges include a first charge range and a plurality of remaining charge ranges. Each remaining charge range is associated with a different combination of upper plates. Electrons are injected onto the floating gate so that the charge on the floating gate falls within the first charge range. To place the charge within one of the remaining charge ranges, electrons are removed from the floating gate by connecting the upper plates that are associated with the desired charge range to the erase voltage to partially erase the transistor.

    摘要翻译： 多位数据存储在可擦除的Frohmann-Bentchkowsky p沟道存储晶体管中，该晶体管具有可切换地连接到擦除电压的多个上板。 多个数据位定义了多个逻辑状态，这些逻辑状态又决定了浮动栅极上的相应电荷范围的数量。 电荷范围包括第一电荷范围和多个剩余电荷范围。 每个剩余电荷范围与上板的不同组合相关联。 将电子注入到浮置栅极上，使得浮置栅极上的电荷落入第一充电范围内。 为了将电荷置于剩余电荷范围之一内，通过将与期望电荷范围相关联的上板连接到擦除电压以将晶体管部分地擦除，从浮置栅极去除电子。

    Schottky diode with reduced size
    37.
    发明授权
    Schottky diode with reduced size 有权
    肖特基二极管尺寸减小

    公开(公告)号：US06380054B1

    公开(公告)日：2002-04-30

    申请号：US09717591

    申请日：2000-11-21

    申请人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

    发明人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

    IPC分类号： H01L2128

    CPC分类号： H01L27/0811

    摘要： The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.

    摘要翻译： 在本发明中，通过形成肖特基二极管通过场氧化物隔离区域，由常规肖特基二极管消耗的硅壳体减少。 通过场氧化物隔离区域的蚀刻需要额外的蚀刻时间，其通过常规蚀刻步骤提供，其通常在接触形成期间指定50-100％的过蚀刻。

    Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture
    39.
    发明授权
    Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture 有权
    具有多晶硅接触插头的介质型反熔丝电池及其制造方法

    公开(公告)号：US06249010B1

    公开(公告)日：2001-06-19

    申请号：US09135536

    申请日：1998-08-17

    申请人： Albert Bergemont ,  Alexander Kalnitsky

    发明人： Albert Bergemont ,  Alexander Kalnitsky

    IPC分类号： H01L31036

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dielectric-based anti-fuse cell and cell array, that include a doped polysilicon contact plug, with a low resistance in the programmed state, a low capacitance, and a small cell area. The dielectric-based anti-fuse cell includes a first insulating layer, typically SiO2, on the surface of a semiconductor substrate. A first doped polysilicon (poly 1) layer is on the upper surface of the first insulating layer and a second insulating layer is over the poly 1 layer. A doped polysilicon contact plug extends through the second insulating layer and into the poly 1 layer. A dielectric layer, typically either an ONO or NO dielectric composite layer, covers the upper surface of the doped polysilicon contact plug. A second doped polysilicon (poly 2) layer is disposed on the dielectric layer. A process for manufacturing the anti-fuse cell and array includes first providing a semiconductor substrate and forming a first insulating layer on its surface. Next a poly 1 layer (e.g. bit lines) is formed on the surface of the first insulating layer followed by the formation of a second insulating layer over the poly 1 layer. A contact opening that extends into the poly 1 layer is then created in the second insulating layer and filled with a doped polysilicon contact plug. Next, a dielectric layer is formed on the upper surface of the doped polysilicon contact plug, followed by the formation of a poly 2 layer (e.g. word lines) on the upper surface of the dielectric layer.

    摘要翻译： 包括掺杂多晶硅接触插头的基于介质的反熔丝电池和电池阵列，其在编程状态下具有低电阻，低电容和小电池区。 基于电介质的抗熔丝单元包括在半导体衬底的表面上的通常为SiO 2的第一绝缘层。 第一掺杂多晶硅（poly 1）层位于第一绝缘层的上表面上，第二绝缘层在聚1层之上。 掺杂多晶硅接触插塞延伸穿过第二绝缘层并进入聚1层。 通常为ONO或NO电介质复合层的电介质层覆盖掺杂多晶硅接触插塞的上表面。 第二掺杂多晶硅（poly 2）层设置在电介质层上。 制造抗熔丝电池和阵列的方法包括首先提供半导体衬底并在其表面上形成第一绝缘层。 接下来，在第一绝缘层的表面上形成聚1层（例如位线），然后在聚1层上形成第二绝缘层。 然后在第二绝缘层中形成延伸到聚1层的接触开口，并填充掺杂的多晶硅接触插塞。 接下来，在掺杂多晶硅接触插塞的上表面上形成电介质层，然后在电介质层的上表面上形成聚二层（例如字线）。