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公开(公告)号：US07495987B2
公开(公告)日：2009-02-24
申请号：US11811547
申请日：2007-06-11
IPC分类号： G11C17/18
摘要： Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.
摘要翻译： 用于读取存储器单元的方法和相应的系统包括从第一电流源进入求和节点的第一电流，其中第一电流源耦合到第一参考。 第二电流源自第二电流源到求和节点，其中第二电流源通过可编程保险丝耦合到第一参考。 第三电流从具有电流吸收器的求和节点沉没，其中电流吸收器耦合到第二参考，并且其中第三电流限制大于第一电流限制并且小于第一电流限制和 第二电流限制。 响应于第一电流，第二电流和第三电流输出求和节点处的电压。 第一和第二电流源，以及电流源可以是电流镜。
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公开(公告)号：US20070247888A1
公开(公告)日：2007-10-25
申请号：US11410584
申请日：2006-04-25
申请人： Andre Vilas Boas , Alfredo Olmos
发明人： Andre Vilas Boas , Alfredo Olmos
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A non-volatile memory cell and method for reading it are disclosed. In one embodiment, the non-volatile memory cell includes a fuse with a first terminal coupled to a first power supply voltage terminal, and a second terminal, a first transistor having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode, and a second transistor having a first current electrode connected to the first power supply voltage terminal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode. By applying a read signal to the control electrode of the first transistor, the state of the cell (blown or unblown) is read.
摘要翻译： 公开了一种非易失性存储单元及其读取方法。 在一个实施例中，非易失性存储单元包括具有耦合到第一电源电压端子的第一端子和第二端子的熔丝，第一晶体管具有耦合到可编程熔丝的第二端子的第一电流电极， 第二电流电极和控制电极，以及具有连接到第一电源电压端子的第一电流电极的第二晶体管，耦合到第一晶体管的控制电极的控制电极和耦合到控制电极的第二电流电极 。 通过对第一晶体管的控制电极施加读取信号，读取单元（吹制或未吹扫）的状态。
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公开(公告)号：US20060268644A1
公开(公告)日：2006-11-30
申请号：US11135963
申请日：2005-05-24
申请人： Andre Boas , Alfredo Olmos
发明人： Andre Boas , Alfredo Olmos
IPC分类号： G11C17/18
摘要： A non-volatile memory cell 100 and method for reading it are disclosed. The system includes a static latch 125 having a first terminal and a second terminal, a first transistor 124 having a first current electrode coupled to said first terminal of said static latch 125 and a fusible element 110 having a first terminal coupled to a second current electrode of the first transistor 125 and a second terminal coupled to a first power supply voltage terminal. In a particular embodiment, the non-volatile memory cell includes a fusible element programming circuit 140 coupled to the first terminal of said fusible element. In another particular embodiment, the non-volatile memory cell includes a cell preset circuit 120 coupled to a control electrode of the first transistor.
摘要翻译： 公开了一种非易失性存储单元100及其读取方法。 该系统包括具有第一端子和第二端子的静态锁存器125，具有耦合到所述静态锁存器125的所述第一端子的第一电流电极的第一晶体管124和具有耦合到第二电流电极的第一端子的可熔元件110 并且耦合到第一电源电压端子的第二端子。 在特定实施例中，非易失性存储单元包括耦合到所述可熔元件的第一端子的可熔元件编程电路140。 在另一特定实施例中，非易失性存储单元包括耦合到第一晶体管的控制电极的单元预置电路120。
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公开(公告)号：US08922287B2
公开(公告)日：2014-12-30
申请号：US13754873
申请日：2013-01-30
摘要： Systems and methods for amplitude loop control for oscillators. In some embodiments, an electronic circuit may include oscillator circuitry configured to produce a periodic signal, and control circuitry operably coupled to the oscillator circuitry, the control circuitry including switched capacitor circuitry configured to determine a difference between maximum and minimum peak voltage values of the periodic signal, the control circuit configured to control a voltage amplitude of the periodic signal based upon the difference. In other embodiments, a method may include receiving a clock signal from a clock generator, determining, using a switched capacitor circuit, a first peak voltage value of the clock signal, determining, using the switched capacitor circuit, a second peak voltage value of the clock signal, and controlling a bias current applied to the clock generator based upon a difference between the first and second peak voltage values.
摘要翻译： 用于振荡器振幅环路控制的系统和方法。 在一些实施例中，电子电路可以包括被配置为产生周期性信号的振荡器电路和可操作地耦合到振荡器电路的控制电路，所述控制电路包括开关电容器电路，其被配置为确定周期性的最大和最小峰值电压值之间的差异 信号，所述控制电路被配置为基于所述差异来控制所述周期信号的电压幅度。 在其他实施例中，一种方法可以包括从时钟发生器接收时钟信号，使用开关电容器电路确定时钟信号的第一峰值电压值，使用开关电容器电路确定第二峰值电压值 并且基于第一和第二峰值电压值之间的差来控制施加到时钟发生器的偏置电流。
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公开(公告)号：US08198937B1
公开(公告)日：2012-06-12
申请号：US13048113
申请日：2011-03-15
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F2200/81 , H03F2203/45514 , H03F2203/45551
摘要： A switched-capacitor amplifier circuit (200 and 300) with rail-to-rail capability without requiring a rail-to-rail operational amplifier includes a switched-capacitor amplifier (202 and 302) and an input network (201) coupled to the switched-capacitor amplifier. The switched-capacitor amplifier includes a non-rail-to-rail operational amplifier (275 and 375). The input network prevents the non-rail-to-rail operational amplifier from receiving an input differential signal that has a common-mode voltage at or near rails of the non-rail-to-rail operational amplifier. Voltages at input terminals of the operational amplifier remain near analog ground, which is an arbitrary voltage level between the rails, during both phases of switching in the switched-capacitor amplifier. In one embodiment, the switched-capacitor amplifier uses a correlated double sampling technique.
摘要翻译： 具有轨到轨能力而不需要轨到轨运算放大器的开关电容放大器电路（200和300）包括开关电容放大器（202和302）和耦合到开关电容器的输入网络（201） 电容放大器。 开关电容放大器包括非轨到轨运算放大器（275和375）。 输入网络防止非轨到轨运算放大器接收在非轨至轨运算放大器的轨道处或其附近具有共模电压的输入差分信号。 在开关电容放大器的开关的两个阶段期间，运算放大器的输入端子处的电压保持靠近模拟地，这是导轨之间的任意电压电平。 在一个实施例中，开关电容放大器使用相关双重采样技术。
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36.发明申请公开(公告)号：US20110121865A1
公开(公告)日：2011-05-26
申请号：US12625982
申请日：2009-11-25
IPC分类号： H03K5/22
CPC分类号： H03K19/00384
摘要： Apparatus, systems and methods are provided for protecting a processing system from electromagnetic interference. An integrated circuit comprises a sensing arrangement configured to sense an interference signal and an interference detection module coupled to the sensing arrangement. The interference detection module is configured to detect when a power level associated with the interference signal is greater than a threshold value. In one embodiment, the interference detection module generates an interrupt for a processing system when the power level associated with the interference signal is greater than the threshold value.
摘要翻译： 提供了用于保护处理系统免受电磁干扰的装置，系统和方法。 集成电路包括被配置为感测干扰信号的感测装置和耦合到感测装置的干扰检测模块。 干扰检测模块被配置为检测与干扰信号相关联的功率电平何时大于阈值。 在一个实施例中，当与干扰信号相关联的功率电平大于阈值时，干扰检测模块产生用于处理系统的中断。
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公开(公告)号：US07839189B2
公开(公告)日：2010-11-23
申请号：US12339938
申请日：2008-12-19
IPC分类号： H03L7/00
CPC分类号： H03K3/0377 , G01R19/0084 , G06F1/28 , G06F1/3203 , H03K17/22
摘要： A voltage detector device is disclosed that includes a coarse-range voltage detector and a fine-range voltage detector. The fine-range voltage detector is configured to remain inactive, so that it consumes a relatively small amount of power, while a monitored voltage is outside a first specified range. In response to determining that the monitored voltage is within the first specified range, the coarse-range voltage detector activates the fine-range voltage detector so that it can monitor the voltage. In response to the fine-voltage monitor determining the voltage falls within a second specified range, the fine-range voltage detector provides a signal to a functional module of an electronic device so that the functional module can provide a defined response, such as executing an interrupt routine.
摘要翻译： 公开了一种包括粗范围电压检测器和精细范围电压检测器的电压检测器装置。 微距电压检测器被配置为保持不活动，使得其消耗相对较小量的功率，而监视的电压在第一指定范围之外。 响应于确定监视电压在第一指定范围内，粗范围电压检测器激活微距电压检测器，使得其可以监测电压。 响应于精细电压监视器确定电压落在第二指定范围内，微距电压检测器向电子设备的功能模块提供信号，使得功能模块可以提供定义的响应，例如执行 中断程序。
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公开(公告)号：US20080304348A1
公开(公告)日：2008-12-11
申请号：US11811547
申请日：2007-06-11
IPC分类号： G11C17/16
摘要： Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.
摘要翻译： 用于读取存储器单元的方法和相应的系统包括从第一电流源进入求和节点的第一电流，其中第一电流源耦合到第一参考。 第二电流源自第二电流源到求和节点，其中第二电流源通过可编程保险丝耦合到第一参考。 第三电流从具有电流吸收器的求和节点沉没，其中电流吸收器耦合到第二参考，并且其中第三电流限制大于第一电流限制并且小于第一电流限制和 第二电流限制。 响应于第一电流，第二电流和第三电流输出求和节点处的电压。 第一和第二电流源，以及电流源可以是电流镜。
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公开(公告)号：US08896349B2
公开(公告)日：2014-11-25
申请号：US13161954
申请日：2011-06-16
IPC分类号： H03K5/153
CPC分类号： G01R19/32 , G01R19/16519 , G01R19/16542 , G01R19/16576
摘要： A low voltage detector (100) includes a power supply voltage monitor circuit (110) that produces a voltage VSP related to a first a power supply voltage, and a voltage generator (105), which includes a plurality of self-cascode MOSFET (SCM) structures (101-103) in a cascade configuration, that generates a reference voltage Vxm. A voltage comparator (140) outputs an output signal in response to a differential between Vxm and VSP, wherein Vxm and VSP have proportional to absolute temperature behavior (PTAT) over temperature with respect to a second power supply voltage. The output signal changes state when the first power supply voltage equals a trip point of the comparator. Each SCM structure is sized to provide a rate of change with temperature of the PTAT behavior of Vxm that matches a rate of change with temperature of the PTAT behavior of VSP.
摘要翻译： 低电压检测器（100）包括产生与第一电源电压相关的电压VSP的电源电压监视电路（110），以及电压发生器（105），其包括多个自共源共栅MOSFET（SCM ）结构（101-103），其产生参考电压Vxm。 电压比较器（140）响应于Vxm和VSP之间的差分输出输出信号，其中Vxm和VSP与温度相对于第二电源电压的绝对温度特性（PTAT）成比例。 当第一电源电压等于比较器的跳变点时，输出信号改变状态。 每个SCM结构的大小可以提供与VMI的PTAT行为的温度的变化率，其与VSP的PTAT行为的温度的变化率匹配。
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公开(公告)号：US20140139201A1
公开(公告)日：2014-05-22
申请号：US13681956
申请日：2012-11-20
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , G01R19/16552 , G06F1/28
摘要： Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.
摘要翻译： 描述了用于低功率电压篡改检测的系统和方法。 在一些实施例中，集成电路可以包括被配置为产生按比例缩小的电源电压的源跟随器电路。 集成电路还可以包括耦合到源跟随器电路的欠压检测电路，欠压检测电路被配置为如果按比例缩小的电源电压大于低阈值电压或第二逻辑值，则输出具有第一逻辑值的第一信号 如果按比例缩小的电源电压小于低阈值电压。 附加地或替代地，集成电路可以包括耦合到源极跟随器电路的过电压检测电路，该过电压检测电路被配置为如果按比例缩小的电源电压小于高阈值电压，则输出具有第一逻辑值的第二信号，或者 如果按比例缩小的电源电压大于高阈值电压，则为第二逻辑值。
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