公开(公告)号：US20040009634A1

公开(公告)日：2004-01-15

申请号：US10194609

申请日：2002-07-12

Applicant: Applied Materials, Inc.

Inventor： Padmapani C. Nallan ,  Ajay Kumar

IPC: H01L021/336

CPC classification number: H01L21/32137 ,  H01L21/28035 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method for fabricating a gate structure having a polysilicon electrode using an oxygen-free chemistry to etch the polysilicon. In one embodiment, the chemistry further comprises nitrogen.

Abstract translation: 一种使用无氧化学制造具有多晶硅电极以蚀刻多晶硅的栅极结构的方法。 在一个实施方案中，化学物质还包含氮。

公开(公告)号：US20030189024A1

公开(公告)日：2003-10-09

申请号：US10118763

申请日：2002-04-08

Applicant: Applied Materials Inc.

Inventor： Anisul Khan ,  Sharma V. Pamarthy ,  Sanjay Thekdi ,  Ajay Kumar

IPC: C23F001/00

CPC classification number: H01L21/30655

Abstract: Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.

Abstract translation: 通过交替蚀刻硅中的开口并在侧壁上沉积共形氟碳聚合物来顺序地制备可变形状的开口。 该聚合物保护开口的侧壁进一步蚀刻。 可以进行各向同性蚀刻以改变蚀刻特征的轮廓，并且用于从硅衬底剥离蚀刻的特征。

公开(公告)号：US20030181056A1

公开(公告)日：2003-09-25

申请号：US10218271

申请日：2002-08-12

Applicant: Applied Materials, Inc.

Inventor： Ajay Kumar ,  Padmapani C. Nallan

IPC: H01L021/302 ,  H01L021/461

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  H01F41/308 ,  H01L43/12

Abstract: A method of etching a film stack that includes at least one layer of magnetic material comprises forming a high temperature mask on the film stack. The film stack is then etched. During the etching process, a residue is formed that comprises components of the high temperature mask. Since the residue and the high temperature mask comprise primarily the same material, the high temperature mask and the residue are simultaneously removed. The method may be used to form a film stack for use in a magneto-resistive random access memory (MRAM) device.

Abstract translation: 蚀刻包括至少一层磁性材料层的薄膜叠层的方法包括在薄膜叠层上形成高温掩模。 然后蚀刻薄膜叠层。 在蚀刻过程中，形成包含高温掩模的部件的残渣。 由于残留物和高温掩模主要由相同的材料组成，所以高温掩模和残余物同时被除去。 该方法可以用于形成用于磁阻随机存取存储器（MRAM）装置中的膜叠层。

公开(公告)号：US20030180968A1

公开(公告)日：2003-09-25

申请号：US10235100

申请日：2002-09-04

Applicant: Applied Materials, Inc.

Inventor： Padmapani C. Nallan ,  Ajay Kumar ,  Jeng H. Hwang ,  Guangxiang Jin ,  Ralph Kerns

IPC: H01L021/00

CPC classification number: H01L23/564 ,  H01L21/67069 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preventing electrical short circuits in a multi-layer magnetic film stack comprises providing a film stack that includes a layer of magnetic material having an exposed surface. A protective layer is deposited on the exposed surface of the magnetic layer. The protective layer may comprise, for example, a fluorocarbon or a hydrofluorocarbon. The film stack is etched and the protective layer protects the exposed surface from a conductive residue produced while etching the film stack. The method may be used in film stacks to form a magneto-resistive random access memory (MRAM) device.

Abstract translation: 一种用于防止多层磁性膜堆叠中的电短路的方法包括提供包括具有暴露表面的磁性材料层的膜堆叠。 保护层沉积在磁性层的暴露表面上。 保护层可以包括例如碳氟化合物或氢氟烃。 蚀刻薄膜叠层并且保护层保护暴露的表面免受在蚀刻薄膜叠层时产生的导电残留物。 该方法可以用于膜堆叠中以形成磁阻随机存取存储器（MRAM）装置。

公开(公告)号：US20030153195A1

公开(公告)日：2003-08-14

申请号：US10076721

申请日：2002-02-13

Applicant: Applied Materials, Inc.

Inventor： Elisabeth Weikmann ,  Aduato Diaz JR. ,  Sharma V. Pamarthy ,  Ajay Kumar ,  Padmapani C. Nallan

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01J37/321 ,  H01J37/32137

Abstract: A method and apparatus for modulating the bias power applied to a wafer support pedestal within a plasma etch reactor. The modulation has an on/off duty cycle of between 10 and 90 percent. Such modulation of the bias power substantially improves the verticality of the etched features located near the edge of a semiconductor wafer as the wafer is being etched in a plasma etch reactor.

Abstract translation: 一种用于调制施加到等离子体蚀刻反应器内的晶片支撑基座的偏置功率的方法和装置。 调制具有10％到90％的开/关占空比。 当在等离子体蚀刻反应器中蚀刻晶片时，偏置功率的这种调制基本上改善了位于半导体晶片的边缘附近的蚀刻特征的垂直度。

公开(公告)号：US20030089457A1

公开(公告)日：2003-05-15

申请号：US09993240

申请日：2001-11-13

Applicant: Applied Materials, Inc.

Inventor： Padmapani C. Nallan ,  Ajay Kumar

IPC: C23C016/00 ,  C23F001/00 ,  H01L021/306 ,  B05C013/00

CPC classification number: H01L21/67248 ,  H01J37/32431 ,  H01J2237/2001 ,  H01L21/67103

Abstract: Apparatus for controlling a thermal conductivity profile of a pedestal in a semiconductor wafer processing system. One embodiment of the apparatus is a thermal shim that is positioned between a wafer retention device (e.g., electrostatic chuck) and a pedestal. The shim controls the thermal conductivity between the wafer retention device and the pedestal. In one embodiment, the thermal shim has a low thermally conductive region and a high thermally conductive region. In a further embodiment, the low thermally conductive region is a hole. By having a hole in the center of the shim, thus forming an annulus, an air gap is formed between the wafer retention device and the pedestal such that less heat will be transferred through the air gap as compared to the high thermally conductive region of the shim.

Abstract translation: 用于控制半导体晶片处理系统中基座的热导率分布的装置。 该装置的一个实施例是位于晶片保持装置（例如，静电卡盘）和基座之间的热垫片。 垫片控制晶片保持装置和基座之间的热导率。 在一个实施例中，热垫片具有低导热区域和高导热区域。 在另一个实施例中，低导热区域是一个孔。 通过在垫片的中心具有孔，从而形成环形空间，在晶片保持装置和基座之间形成气隙，使得较少的热量将通过空气间隙传递， 垫片

公开(公告)号：US20030077878A1

公开(公告)日：2003-04-24

申请号：US10035372

申请日：2001-10-19

Applicant: Applied Materials, Inc.

Inventor： Ajay Kumar ,  Padmapani C. Nallan ,  Anisul Khan ,  Dragan V. Podlesnik

IPC: H01L021/301 ,  H01L021/46 ,  H01L021/78

CPC classification number: H01L21/304 ,  H01L21/78

Abstract: A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.