公开(公告)号：US20230289405A1

公开(公告)日：2023-09-14

申请号：US18016916

申请日：2021-07-19

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Balaji Venu

IPC: G06F18/2415 ,  G06F17/11

CPC classification number: G06F18/2415 ,  G06F17/11

Abstract: An entropy calculation for certainty-based classification networks is provided. An integer operand p is received. A remainder portion of the integer operand p is determined based on a range reduction operation. A scaled integer operand is determined based on the integer operand p. An index for a data structure, such as, for example, a look-up table (LUT), is determined based on the remainder portion of the integer operand p and a parameter N associated with the data structure. A data structure value in the data structure is looked up based on the index. A scaled entropy value is generated by adding the data structure value to the scaled integer operand. An entropy value is determined based on the scaled entropy value, and the entropy value is output.

公开(公告)号：US11693665B2

公开(公告)日：2023-07-04

申请号：US17754739

申请日：2020-09-28

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Michiel Willem Van Tol

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3838

Abstract: A data processing apparatus and method of operating such is disclosed. Issue circuitry buffers operations prior to execution until operands are available in a set of registers. A first and a second load operation are identified in the issue circuitry, when both are dependent on a common operand, and when the common operand is available in the set of registers. Load circuitry has a first address generation unit to generate a first address for the first load operation and a second address generation unit to generate a second address for the second load operation. An address comparison unit compares the first address and the second address. The load circuitry is arranged to cause a merged lookup to be performed in local temporary storage, when the address comparison unit determines that the first and the second address differ by less than a predetermined address range characteristic of the local temporary storage.

公开(公告)号：US11321051B2

公开(公告)日：2022-05-03

申请号：US16417840

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Emre Özer ,  Jedrzej Kufel ,  Mbou Eyole ,  John Philip Biggs

IPC: G06F17/18 ,  G06F7/544 ,  G06F7/60 ,  G06F7/22

Abstract: Apparatuses, methods of operating apparatuses, and corresponding computer programs are disclosed. In the apparatuses input circuitry receives input data comprising at least one data element and shift circuitry generates, for each data element of the input data, a bit-map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit-map is dependent on the data element. Summation circuitry generates a position summation value for each position in the bit-map, wherein each position summation value is a sum across all bit-maps generated by the shift circuitry from the input data. Maximum identification circuitry determines at least one largest position summation value generated by the summation circuitry and output circuitry to generate an indication of at least one data element corresponding to the at least one largest position summation value. The statistical mode of the data elements in the input data is thereby efficiently determined.

公开(公告)号：US11263073B2

公开(公告)日：2022-03-01

申请号：US16641377

申请日：2018-08-30

Applicant: ARM Limited

Inventor： Matthias Lothar Boettcher ,  Mbou Eyole ,  Balaji Venu

IPC: G06F11/07 ,  G06F9/22

Abstract: An apparatus has a processing pipeline (2) comprising an execute stage (30) and at least one front end stage (10), (20), (25) for controlling which micro operations are issued to the execute stage. The pipeline has an intra-core lockstep mode of operation in which the at least one front end stage (10), (20), (25) issues micro operations for controlling the execute stage (30) to perform main processing and checker processing. The checker processing comprises redundant operations corresponding to associated main operations of at least part of the main processing. Error handling circuitry (200), (210) is responsive to the detection of a mismatch between information associated with given checker and main operations to trigger a recovery operation to correct an error and continue forward progress of the main processing.

公开(公告)号：US11061852B2

公开(公告)日：2021-07-13

申请号：US16645993

申请日：2018-09-25

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Emre Ozer ,  Xabier Iturbe ,  Shidhartha Das

IPC: G11C7/00 ,  G06F15/78 ,  G11C14/00 ,  H03K19/17728 ,  G06F15/76

Abstract: A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

公开(公告)号：US11042375B2

公开(公告)日：2021-06-22

申请号：US15665781

申请日：2017-08-01

Applicant: ARM Limited

Inventor： Mbou Eyole ,  Jesse Garrett Beu ,  Alejandro Martinez Vicente ,  Timothy Hayes

IPC: G06F9/30

Abstract: An apparatus and method of operating the apparatus are provided for performing a count operation. Instruction decoder circuitry is responsive to a count instruction specifying an input data item to generate control signals to control the data processing circuitry to perform a count operation. The count operation determines a count value indicative of a number of input elements of a subset of elements in the specified input data item which have a value which matches a reference value in a reference element in a reference data item. A plurality of count operations may be performed to determine a count data item corresponding to the input data item. A register scatter storage instruction, a gather index generation instruction, and respective apparatuses responsive to them, as well as simulator implementations, are also provided.

公开(公告)号：US10922084B2

公开(公告)日：2021-02-16

申请号：US16331179

申请日：2017-08-14

Applicant: ARM LIMITED

Inventor： Matthew James Horsnell ,  Mbou Eyole

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54

Abstract: An apparatus has processing circuitry supporting vector load and store instructions. In response to a transaction start event, the processing circuitry executes one or more subsequent instructions speculatively. In response to a transaction end event, the processing circuitry commits speculative results of those instructions. Hazard detection circuitry detects whether an inter-element address hazard occurs between an address for data element J for an earlier vector load instruction and an address for data element K for a later vector store instruction, where K and J are not equal. In response to detecting the inter-element address hazard, the hazard detection circuitry triggers the processing circuitry to abort further processing of the instructions following the transaction start event and to prevent the speculative results being committed. This approach can provide faster performance for vectorised code.

公开(公告)号：US10678540B2

公开(公告)日：2020-06-09

申请号：US15973663

申请日：2018-05-08

Applicant: Arm Limited

Inventor： Jacob Eapen ,  Mbou Eyole ,  Neil Burgess

IPC: G06F9/30

Abstract: An apparatus and method are provided for efficiently performing arithmetic operations that include at least a multiplication operation. The apparatus comprises processing circuitry to perform data processing operations, and instruction decode circuitry responsive to program instructions to generate control signals to control the processing circuitry to perform the data processing operations. In response to an arithmetic operation with shift instruction specifying performance of an arithmetic operation comprising at least a multiplication operation, and having a field which provides a programmable shift indication, the instruction decode circuitry is configured to control the processing circuitry to perform the arithmetic operation during which an intermediate value is produced, and to select a target portion of the intermediate value based on an output window determined from the programmable shift indication.

公开(公告)号：US10437594B2

公开(公告)日：2019-10-08

申请号：US15746559

申请日：2016-06-15

Applicant: ARM LIMITED

Inventor： Mbou Eyole ,  Matthias Lothar Boettcher

IPC: G06F9/30 ,  G06F9/38 ,  G06F3/06 ,  G06F15/80

Abstract: An apparatus and method are provided for transferring a plurality of data structures from memory into one or more vectors of data elements stored in a register bank. The apparatus has first interface circuitry to receive data structures retrieved from memory, where each data structure has an associated identifier and comprises N data elements. Multi-axial buffer circuitry is provided having an array of storage elements, where along a first axis the array is organized as N sets of storage elements, each set containing a plurality VL of storage elements, and where along a second axis the array is organized as groups of N storage elements, with each group containing a storage element from each of the N sets. Access control circuitry then stores the N data elements of a received data structure in one of the groups selected in dependence on the associated identifier. Responsive to an indication that all required data structures have been stored in the multi-axial buffer circuitry, second interface circuitry then outputs the data elements stored in one or more of the sets of storage elements as one or more corresponding vectors of data elements for storage in a register bank, each vector containing VL data elements. Such an approach can significantly increase the performance of handling such load operations, and give rise to potential energy savings.

公开(公告)号：US12265603B2

公开(公告)日：2025-04-01

申请号：US17429222

申请日：2019-07-26

Applicant: Arm Limited

Inventor： Daren Croxford ,  Roberto Lopez Mendez ,  Mbou Eyole ,  Matthew James Horsnell

IPC: G06F21/00 ,  A61B5/00 ,  A61B5/117 ,  A61B5/378 ,  A61B5/38 ,  G06F21/36

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques for authenticating an identity of a subject. In particular, some embodiments are directed to techniques for authentication of an identity of a subject as being an identity of a particular unique individual based, at least in part, on involuntary responses by the subject to sensory stimuli.