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31.
公开(公告)号:US09704914B2
公开(公告)日:2017-07-11
申请号:US14913174
申请日:2015-07-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Shi Shu , Jincheng Gao , Chuanxiang Xu , Feng Zhang
IPC: H01L27/146 , H01L27/144 , H01L31/02 , H01L31/0224 , H01L31/0232 , H01L31/115
Abstract: An array substrate and manufacturing method thereof, an X-ray flat panel detector and an image pickup system are provided. The array substrate is divided into a plurality of detection units, and each of the detection units has a first electrode and a photoelectric conversion structure provided therein. The first electrode is disposed on a side of the photoelectric conversion structure opposite to a light incident side, and is electrically connected to the photoelectric conversion structure. A reflective layer that is electrically conductive is further included between the first electrode and the photoelectric conversion structure, and a surface of the reflective layer facing the photoelectric conversion structure is a reflection surface. The utilization rate of light can be enhanced by the array substrate as stated in embodiments of the invention, so that the detection accuracy of the X-ray flat panel detector is enhanced.
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公开(公告)号:US12217637B2
公开(公告)日:2025-02-04
申请号:US17791226
申请日:2021-08-27
Applicant: BOE Technology Group Co., Ltd.
Inventor: Yang Yue , Wei Wang , Ruoyu Ma , Shunhang Zhang , Chuanxiang Xu , Xiang Li , Yong Yu , Shi Shu , Qi Yao
Abstract: The present disclosure provides a display backplane and a preparation method therefor, and a display apparatus. The display backplane includes a plurality of display units, at least one display unit includes a pixel area and a light transmitting area, the pixel area is configured to perform image display and the light transmitting area is configured to transmit light; and in a plane perpendicular to the display backplane, the light transmitting area includes a substrate and a light transmitting structure layer arranged on the substrate, and the light transmitting structure layer is provided with light transmitting holes.
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公开(公告)号:US12114535B2
公开(公告)日:2024-10-08
申请号:US17428630
申请日:2020-10-19
Applicant: BOE Technology Group Co., Ltd.
Inventor: Yang Yue , Shi Shu , Qi Yao , Wei Huang , Haitao Huang , Shipei Li , Yong Yu , Xiang Li , Chuanxiang Xu , Wenqu Liu
IPC: H10K59/122 , G02B5/20
CPC classification number: H10K59/122 , G02B5/201
Abstract: A counter substrate is provided. The counter substrate includes a bank layer on a base substrate and defining a plurality of bank apertures; a quantum dots material layer on the base substrate, the quantum dots material layer including a plurality of quantum dots blocks respectively in at least some of the plurality of bank apertures; and a support layer on a side of the quantum dots material layer and the bank layer away from the base substrate. The support layer includes one or more support portions, orthographic projections of which on the base substrate adjacent to a periphery of an orthographic projection of a respective one of the plurality of bank apertures on the base substrate. An orthographic projection of the bank layer on the base substrate at least partially overlaps with an orthographic projection of the support layer on the base substrate.
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34.
公开(公告)号:US20240047363A1
公开(公告)日:2024-02-08
申请号:US17762239
申请日:2021-05-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Yang Yue , Shi Shu , Qi Yao , Yong Yu , Shipei Li , Xiang Li , Chuanxiang Xu , Wenqu Liu , Renquan Gu , Haitao Huang
IPC: H01L23/538 , H01L25/075 , H01L21/48
CPC classification number: H01L23/5383 , H01L25/0753 , H01L21/4857
Abstract: A manufacturing method of a displaying base plate, a displaying base plate and a displaying apparatus. The displaying base plate includes an active area and a peripheral area located at a periphery of the active area. The displaying base plate includes: a substrate; a wiring functional layer disposed on one side of the substrate, wherein the wiring functional layer includes a metal wiring and bonding terminals connected to the metal wiring), the bonding terminals include a first bonding terminal, a second bonding terminal and a third bonding terminal, the first bonding terminal and the second bonding terminal are located at the active area, and the third bonding terminal is located at the peripheral area; a first passivation layer disposed on one side of the wiring functional layer that is away from the substrate; and a light shielding layer disposed on one side of the first passivation layer that is away from the substrate.
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公开(公告)号:US11832495B2
公开(公告)日:2023-11-28
申请号:US17628516
申请日:2021-03-09
Applicant: BOE Technology Group Co., Ltd.
Inventor: Yong Yu , Shi Shu , Qi Yao , Guangcai Yuan , Chuanxiang Xu , Yang Yue , Haitao Huang , Xiang Li
IPC: H10K59/38 , G02F1/1343 , G02F1/1335 , G02F1/13357 , H10K50/86 , H10K59/122 , H10K59/12 , G02F1/1362
CPC classification number: H10K59/38 , G02F1/133504 , G02F1/133512 , G02F1/133514 , G02F1/133603 , G02F1/133621 , G02F1/134345 , H10K50/865 , G02F1/1362 , G02F2201/52 , G02F2202/046 , G02F2202/36 , H10K59/1201 , H10K59/122
Abstract: Provided are a display apparatus and a manufacturing method therefor, the display apparatus comprising: a plurality of mutually independent subpixel regions; a light source (101), light emitted from the light source (101) illuminating the subpixel regions; and a light control layer (102), which is located on a light exiting side of the light source (101), the light control layer (102) comprising: color conversion structures (1021) located at the subpixel regions, the color conversion structures (1021) each comprising a nanoporous material and at least a color conversion material distributed among the nanoporous material, the color conversion material being used to convert light emitted from the light source (101) into light of a color corresponding to the subpixel region where the light is located.
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公开(公告)号:US11785825B2
公开(公告)日:2023-10-10
申请号:US17210733
申请日:2021-03-24
Applicant: BOE Technology Group Co., Ltd.
Inventor: Haitao Huang , Shi Shu , Qi Yao , Chuanxiang Xu , Zhao Cui , Lina Jing , Renquan Gu , Yong Yu
IPC: H10K59/38 , H10K50/854 , H10K50/856 , H10K50/86 , H10K59/12 , H10K102/00
CPC classification number: H10K59/38 , H10K50/854 , H10K50/856 , H10K50/865 , H10K59/12 , H10K2102/331
Abstract: A display panel is provided with a plurality of sub-pixel areas and includes: a base substrate, a light emitting structure including a plurality of light emitting devices corresponding to the sub-pixel areas, an encapsulating layer, and a pixel defining layer. The pixel defining layer includes: a plurality of openings; at least two sub-pixel defining layers, and a quantum dot color film layer. Each of the sub-pixel defining layers is provided with a pixel separator. The pixel separators fence each of the plurality of openings, and define the plurality of sub-pixel areas. In the at least two sub-pixel defining layers, the sectional shape of the pixel separator in the sub-pixel defining layer which is farthest away from the encapsulating layer includes a regular trapezoid. The quantum dot color film layer includes a plurality of quantum dot color films arranged in the corresponding openings.
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公开(公告)号:US11719983B2
公开(公告)日:2023-08-08
申请号:US16986748
申请日:2020-08-06
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Yang Yue , Qi Yao , Yong Yu , Hua Huang , Tong Yang , Shi Shu , Chuanxiang Xu , Xue Jiang , Haitao Huang , Xiang Li , Zhao Cui
IPC: G02F1/1347 , G02F1/1335 , G02F1/13357 , G02F1/1339 , G02F1/1343 , G02F1/1362
CPC classification number: G02F1/1347 , G02F1/13394 , G02F1/13396 , G02F1/13398 , G02F1/13471 , G02F1/133512 , G02F1/133514 , G02F1/133528 , G02F1/133617 , G02F1/134309 , G02F1/136286 , G02F1/133548 , G02F1/133614 , G02F2201/121 , G02F2201/123
Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes: a first medium and a first spacer wall between the first substrate and the second substrate, wherein the first sub-panel has filter pixels arranged at intervals, the first spacer wall is black and arranged along spaces between filter pixels, and a dielectric coefficient of the first spacer wall is greater than that of the first medium; and a second sub-panel on a light emergent side of the first sub-panel and including a second medium and a second spacer wall between the third substrate and the fourth substrate, wherein the second sub-panel has display pixels arranged at intervals, the second spacer wall is black and arranged along spaces between display pixels, and a dielectric coefficient of the second spacer wall is greater than that of the second medium.
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公开(公告)号:US11489028B2
公开(公告)日:2022-11-01
申请号:US16943689
申请日:2020-07-30
Applicant: BOE Technology Group Co., Ltd.
Inventor: Chuanxiang Xu , Shi Shu , Qi Yao
Abstract: The disclosure provides a display substrate, a fabrication method thereof and a display device. The display substrate includes a base, and has a display area and a frame area. The method includes: forming an active region of a thin film transistor in the display area; forming a first lead in the frame area; forming a buffer layer directly covering the first lead; forming a connection via hole communicating with the active region; forming a protective layer directly covering the buffer layer in the frame area; cleaning the active region exposed by the connection via hole after forming the protective layer; removing the protective layer in the frame area after cleaning; and forming a second lead in the frame area after removing the protective layer, an orthographic projection of the second lead on the base and an orthographic projection of the first lead on the base at least partially overlap.
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39.
公开(公告)号:US20220317513A1
公开(公告)日:2022-10-06
申请号:US17419685
申请日:2020-09-29
Applicant: BOE Technology Group Co., Ltd.
Inventor: Haitao Huang , Shi Shu , Chuanxiang Xu , Liuqing Li , Zhao Cui , Renquan Gu
IPC: G02F1/1335 , G02F1/1343 , G02F1/1368 , H01L27/32 , H01L51/56 , G03F7/00 , C23C16/26 , C23C16/50
Abstract: A display panel is provided. The display panel includes a bank layer and a quantum dots material layer on a base substrate. The bank layer defines a plurality of bank apertures. The quantum dots material layer includes a plurality of quantum dots blocks respectively in at least some of the plurality of bank apertures. At least a portion of the bank layer between two adjacent bank apertures includes a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface closer to a first bank aperture, and a fourth surface connecting the first surface and the second surface closer to a second bank aperture. At least a portion of a third surface or a fourth surface of a portion of the bank layer between two adjacent bank apertures is a wavy surface including alternating convex and concave portions.
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公开(公告)号:US11442583B2
公开(公告)日:2022-09-13
申请号:US16966394
申请日:2020-01-17
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Wenqu Liu , Xiufeng Li , Qi Yao , Feng Zhang , Liwen Dong , Zhao Cui , Chuanxiang Xu , Detian Meng , Xiaoxin Song , Libo Wang , Yang Yue , Dongfei Hou , Zhijun Lv
IPC: G06F3/043 , H01L41/04 , H01L41/047 , H01L41/083 , H01L41/113 , H01L41/27 , G06F3/044 , G06F3/041 , G06V40/13 , G06V40/12
Abstract: A fingerprint identification module, a manufacturing method thereof and an electronic device are disclosed. In the fingerprint identification module, an auxiliary structure is at least partially located on a functional substrate, and a plurality of first driving electrodes are on a side, away from the functional substrate, of the piezoelectric material and the auxiliary structure; each first driving electrode extends along a first direction and exceeds a first edge of the piezoelectric material layer in the first direction; the plurality of first driving electrodes are arranged at intervals along a second direction; the auxiliary structure is at least in contact with the first edge; the auxiliary structure includes a slope portion; and a thickness of the slope portion in a direction perpendicular to the functional substrate gradually decreases in a direction from the first edge to a position away from a center of the piezoelectric material layer.
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