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    BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HOT) DIRECT SILICON BONDED (DSB) SUBSTRATES
    34.
    发明申请
    BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HOT) DIRECT SILICON BONDED (DSB) SUBSTRATES 有权
    混合定向技术（热）直接硅粘结（DSB）基板的边界区域缺陷减少

    公开(公告)号：US20100032727A1

    公开(公告)日：2010-02-11

    申请号：US12538048

    申请日：2009-08-07

    申请人： Haowen Bu ,  Shaofeng Yu ,  Angelo Pinto ,  Ajith Varghese

    发明人： Haowen Bu ,  Shaofeng Yu ,  Angelo Pinto ,  Ajith Varghese

    IPC分类号： H01L27/092 ,  H01L21/20 ,  H01L21/8238

    CPC分类号： H01L21/26506 ,  H01L21/187 ,  H01L21/324 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/045 ,  H01L29/665

    摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.

    摘要翻译： 用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。 （100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。 本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。 从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。 退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。 还公开了用本发明方法形成的集成电路。

    DUAL POLY DEPOSITION AND THROUGH GATE OXIDE IMPLANTS
    35.
    发明申请
    DUAL POLY DEPOSITION AND THROUGH GATE OXIDE IMPLANTS 审中-公开
    双重沉积物和通过浇注氧化物的植入物

    公开(公告)号：US20080315328A1

    公开(公告)日：2008-12-25

    申请号：US12204072

    申请日：2008-09-04

    申请人： Shaofeng Yu ,  Shyh-Horng Yang

    发明人： Shaofeng Yu ,  Shyh-Horng Yang

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823892 ,  H01L21/823842 ,  H01L21/823857

    摘要： Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.

    摘要翻译： 掺杂剂通过栅极电极材料和栅极电介质层的薄层以相对高的能量注入到半导体衬底的未屏蔽的第一区域中。 然后将较低能量的掺杂剂注入到栅极电极材料的薄层中。 然后掩蔽第一区域，并且该过程在半导体衬底的先前掩蔽的但现在未掩模的第二区域中重复。 然后在栅电极材料的薄层上形成第二（通常较厚）的栅电极材料层。 将厚栅极电极材料层，薄栅电极材料层和栅极电介质材料层图案化以在衬底的掺杂区域上形成一个或多个栅极结构。 源极和漏极区域形成在与栅极结构相邻的衬底区域中以建立一个或多个MOS晶体管。

    FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN
    36.
    发明申请
    FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN 审中-公开
    具有完全硅化物电极和通道应变的晶体管的制造

    公开(公告)号：US20080283941A1

    公开(公告)日：2008-11-20

    申请号：US12173518

    申请日：2008-07-15

    申请人： Michael Francis Pas ,  Shaofeng Yu

    发明人： Michael Francis Pas ,  Shaofeng Yu

    IPC分类号： H01L29/00

    CPC分类号： H01L21/823814 ,  H01L21/28097 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

    摘要： An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about 3:1. The source and drain structures are located in openings of the substrate and adjacent to the gate electrode. The source and drain structures are filled with SiGe to produce stress in the transistor channel region.

    摘要翻译： 集成电路包括在半导体衬底上或半导体衬底中的一个或多个晶体管。 至少一个晶体管包括栅极电极和源极和漏极结构。 栅电极具有完全硅化的栅极电极层，Ni:Si的比例范围为约2:1至约3:1。 源极和漏极结构位于衬底的开口中并且邻近栅电极。 源极和漏极结构充满SiGe以在晶体管沟道区域产生应力。

    Low cost transistors using gate orientation and optimized implants
    38.
    发明授权
    Low cost transistors using gate orientation and optimized implants 有权
    低成本晶体管采用栅极取向和优化的植入

    公开(公告)号：US08405154B2

    公开(公告)日：2013-03-26

    申请号：US13167538

    申请日：2011-06-23

    申请人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

    发明人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

    IPC分类号： H01L21/70

    CPC分类号： H01L21/823437 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659

    摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

    摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。

    LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS
    40.
    发明申请
    LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS 有权
    低成本晶体管使用门方向和优化的植入

    公开(公告)号：US20100327374A1

    公开(公告)日：2010-12-30

    申请号：US12492743

    申请日：2009-06-26

    申请人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

    发明人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

    IPC分类号： H01L27/088 ,  H01L21/77 ,  H01L21/265

    CPC分类号： H01L21/823437 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659

    摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

    摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电性质的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。