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公开(公告)号：US20130130511A1
公开(公告)日：2013-05-23
申请号：US13473439
申请日：2012-05-16
IPC分类号： H01L21/027
CPC分类号： H01L23/528 , G03F7/70383 , G06F17/5068 , H01L21/027 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/105
摘要： A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.
摘要翻译： 掩模材料层沉积在基底上。 以光栅化的线性图案，并且根据基于要在衬底上形成的导电结构段的节距的扫描间距扫描掩模材料上的能量束。 能量束被定义为将能量束入射到其上的掩模材料变换成可移除状态。 在通过掩模材料扫描能量束时，能量束在基板上要形成导电结构的位置处被接通，并且能量束在不导电结构的位置被切断 形成在基板上。
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公开(公告)号：US08286107B2
公开(公告)日：2012-10-09
申请号：US12340406
申请日：2008-12-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： Selected cells in a semiconductor chip layout are replaced with corresponding PCT pre-processed cells. Each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments. Following replacement of the selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, a chip-wide PCT processing operation is performed on the semiconductor chip layout for a given chip level. The presence of the PCT pre-processed cells in the semiconductor chip layout serves to accelerate the chip-wide PCT processing of the semiconductor chip layout. The chip-wide PCT processed semiconductor layout for the given chip level is recorded on a persistent storage medium.
摘要翻译： 半导体芯片布局中的选定单元被相应的PCT预处理单元替换。 每个PCT预处理小区表示先前已经进行细胞级PCT处理操作的特定选择的细胞，以便包括基于PCT的细胞布局调整。 在用相应的PCT预处理单元替换半导体芯片布局中的所选单元之后，针对给定的芯片级对半导体芯片布局执行芯片宽的PCT处理操作。 半导体芯片布局中的PCT预处理电池的存在用于加速半导体芯片布局的芯片宽的PCT处理。 用于给定芯片级的芯片宽的PCT处理的半导体布局被记录在永久存储介质上。
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33.发明授权Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances 有权半导体器件包括至少六个晶体管，形成包括至少两个不同的栅极接触连接距离的线性形状公开(公告)号：US08264007B2
公开(公告)日：2012-09-11
申请号：US12572046
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 半导体器件的单元包括形成为包括多个扩散区域的基板部分，该多个扩散区域包括至少一个p型扩散区域和至少一个由一个或多个非有源区域彼此分离的n型扩散区域。 电池包括包括多个导电特征的栅电极层，该导电特征限定为只在第一平行方向上延伸。 栅极电极层中的每个导电特征由相应的起始矩形布局特征制成。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 单元中的PMOS和NMOS晶体管器件的总数大于或等于8。 电池还包括形成在栅极电极上方的多个互连电平。
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34.发明授权Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact 有权半导体器件包括至少六个晶体管，其形成包括至少两个晶体管的线性形状，所述晶体管形成具有不同于延伸距离的栅极接触的线性形状公开(公告)号：US08258550B2
公开(公告)日：2012-09-04
申请号：US12572068
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.
摘要翻译： 半导体器件的单元布局包括包括多个扩散区布局形状的扩散级布局。 电池布局还包括限定为包括仅在第一平行方向上延伸的线性布局特征的栅极电平布局。 在第一并行方向上共享共同的范围的相邻线性布局特征通过栅电极级布局基本上相等的端到端间隔相互分开，并且被最小化到由 半导体器件制造能力。 栅电极级布局包括沿着沿着第一并行方向的至少四个不同的线段限定的线性布局特征。 电池布局还包括多个互连电平布局，每个互连电平布局被定义为在电池的栅电极电平以上的相应互连电平内对导电特征进行图案化。
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35.发明授权Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region 有权具有栅极电平的半导体器件包括第一类型的四个晶体管和第二类型的四个晶体管，由非扩散区域隔开，并且在分离非扩散区域上具有限制的栅极接触放置公开(公告)号：US08258548B2
公开(公告)日：2012-09-04
申请号：US12571998
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 半导体器件的单元包括形成为包括多个扩散区域的基板部分，该多个扩散区域包括至少一个p型扩散区域和至少一个由一个或多个非有源区域彼此分离的n型扩散区域。 电池包括包括多个导电特征的栅电极层，该导电特征限定为只在第一平行方向上延伸。 栅极电极层中的每个导电特征由相应的起始矩形布局特征制成。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 多个PMOS晶体管器件等于电池栅极电平中的NMOS晶体管器件的数量。 电池还包括形成在栅极电极上方的多个互连电平。
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36.发明授权Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type 有权集成电路，包括栅极电平区域，其包括至少三个相等长度的线性导电结构，其具有对准的端部并以相等间距定位，并形成不同类型的晶体管的多个栅电极公开(公告)号：US08217428B2
公开(公告)日：2012-07-10
申请号：US12571351
申请日：2009-09-30
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within the gate electrode level is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 公开了一种半导体器件的电池，其包括扩散级，其包括由非活性区域分开的多个扩散区域。 电池还包括栅极电极级，其包括限定为仅在第一平行方向上延伸的多个导电特征。 栅极电极层中的每个导电特征由相应的起始矩形布局特征制成。 栅极电极级包括沿着沿着第一平行方向的至少四个不同的虚拟线限定的导电特征。 栅电极层中的导电特征的宽度垂直于第一平行方向被测量，并且小于在光刻工艺中用于制造导电特征的光的波长。 电池还包括形成在栅极电极上方的多个互连电平。
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37.发明授权Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistor 有权集成电路包括至少三个不同长度的线性导电结构，每个形成不同晶体管的栅极公开(公告)号：US08138525B2
公开(公告)日：2012-03-20
申请号：US12572061
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 半导体器件的单元包括形成为包括至少一个p型扩散区域和由非有源区域分隔开的至少一个n型扩散区域的衬底部分。 电池包括包括多个导电特征的栅电极层，该导电特征限定为只在第一平行方向上延伸。 栅极电极层中的每个导电特征由相应的起始矩形布局特征制成。 在栅电极水平内的五波长光刻相互作用半径内的导电特征的宽度尺寸小于193纳米的光的波长。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 单元中的PMOS和NMOS晶体管器件的总数大于或等于8。 电池还包括形成在栅极电极上方的多个互连电平。
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38.发明授权Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends 有权具有栅极电平区域的集成电路，其包括至少七个线性形状的导电结构，其等间距包括形成两种不同类型的晶体管的线性导电结构和至少三个具有对齐端的线形导电结构公开(公告)号：US08134185B2
公开(公告)日：2012-03-13
申请号：US12567654
申请日：2009-09-25
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout corresponding to an entire gate level of the cell. The gate electrode layout includes a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.
摘要翻译： 公开了半导体器件的单元的布局，以包括扩散级布局，其包括多个扩散区域布局形状，包括由中心非活性区域分隔的p型和n型扩散区域。 单元的布局包括对应于单元的整个栅极电平的栅极电平布局。 栅电极布局包括多个线性布局特征，其放置以仅在第一平行方向上延伸。 限制布局区域的栅极电平布局中的线形布局特征中的每一个都是矩形的。 栅极电平布局内的线形布局特征在p型和/或n型扩散区中的一个或多个上延伸以形成PMOS和NMOS晶体管器件。 单元中的PMOS和NMOS晶体管器件的总数大于或等于8。
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39.发明授权Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different size 有权集成电路包括具有栅极部分和不同尺寸的延伸部分的线性导电结构公开(公告)号：US08134183B2
公开(公告)日：2012-03-13
申请号：US12567616
申请日：2009-09-25
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.
摘要翻译： 半导体器件包括其中限定有多个扩散区的衬底部分。 在基板部分上方形成栅极电平区域，以包括仅在第一平行方向上延伸的导电特征。 共享公共线程的相邻的导电特征由相应的起始布局特征制成，该特征通过栅极电极水平区域上的基本相等和最小尺寸的端到端间隔彼此分开。 在5波长光刻相互作用半径内的导电特征的宽度小于在其制造的光刻工艺中使用的193纳米波长的光。 一些导电特征在多个扩散区域上延伸以形成PMOS或NMOS晶体管器件。 栅极电极区域中的PMOS和NMOS晶体管器件的总数大于或等于8。
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40.发明授权Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length 有权集成电路包括至少六个线性形状的导电结构结构，其等间距包括具有不同长度的非栅极部分的至少两个线状导电结构公开(公告)号：US08129757B2
公开(公告)日：2012-03-06
申请号：US12572239
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication.
摘要翻译： 半导体器件的单元包括扩散级，包括由非活性区分隔的多个扩散区。 电池还包括栅极电极级，其包括限定为仅在第一平行方向上延伸的导电特征。 导电特征中相邻的导电特征在第一平行方向上共享公共线的范围由相应的起始布局特征制成，所述特征通过端对端间隔彼此分开，所述端对端间隔的尺寸基本相等并且最小化 栅电极电平。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 单元中的PMOS和NMOS晶体管器件的总数大于或等于8。 栅电极层中的导电特征的宽度小于在其制造的光刻工艺中使用的光的波长。
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