公开(公告)号：US20220157975A1

公开(公告)日：2022-05-19

申请号：US17606216

申请日：2020-03-31

Applicant: SOUTHEAST UNIVERSITY

Inventor： Jing ZHU ,  Ankang LI ,  Long ZHANG ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

IPC: H01L29/739 ,  H01L29/10

Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

公开(公告)号：US20210174184A1

公开(公告)日：2021-06-10

申请号：US17181595

申请日：2021-02-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Ziyu LI ,  Jun YANG ,  Longxing SHI

IPC: G06N3/063 ,  G06N3/04

Abstract: The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.

公开(公告)号：US20180234007A1

公开(公告)日：2018-08-16

申请号：US15751136

申请日：2016-01-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Shen XU ,  Chong WANG ,  Xianjun FAN ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

IPC: H02M1/08 ,  G05B19/042

CPC classification number: H02M1/08 ,  G05B19/042 ,  G05B2219/2639 ,  H02M3/335 ,  H02M2001/0048

Abstract: A control method for improving dynamic response of switch power is based on a closed-loop control system comprising a sampling module, a dynamic control module, an error calculation module, a PID module, a mode control module, and a PWM module. The sampling module samples an output voltage Vo, and the dynamic control module compares the output voltage Vo with a set maximum voltage Vomax, a set minimum voltage Vomin, and a reference voltage Vref, so as to determine whether to adopt a dynamic mode. In the dynamic mode, when the output voltage Vo changes greatly, the output voltage Vo is rapidly restored to a stable voltage by inputting large power or small power.

公开(公告)号：US20180174942A1

公开(公告)日：2018-06-21

申请号：US15576850

申请日：2016-01-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang LIU ,  Ning WANG ,  Jiaxing WEI ,  Chao LIU ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

IPC: H01L23/367 ,  H01L25/18 ,  H01L23/31 ,  H01L23/495 ,  H01L25/16

CPC classification number: H01L23/3675 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/1426 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.