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    Barrier structure for semiconductor devices
    31.
    发明授权
    Barrier structure for semiconductor devices 有权
    半导体器件的阻挡结构

    公开(公告)号：US07193327B2

    公开(公告)日：2007-03-20

    申请号：US11042396

    申请日：2005-01-25

    申请人： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

    发明人： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

    摘要翻译： 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。

    Barrier structure for semiconductor devices
    33.
    发明申请
    Barrier structure for semiconductor devices 有权
    半导体器件的阻挡结构

    公开(公告)号：US20060163746A1

    公开(公告)日：2006-07-27

    申请号：US11042396

    申请日：2005-01-25

    申请人： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

    发明人： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

    IPC分类号： H01L23/48

    CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

    摘要翻译： 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。

    Barrier layer and fabrication method thereof
    34.
    发明申请
    Barrier layer and fabrication method thereof 有权
    阻挡层及其制造方法

    公开(公告)号：US20060068604A1

    公开(公告)日：2006-03-30

    申请号：US10955519

    申请日：2004-09-30

    申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76826 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A barrier layer and a fabrication thereof are disclosed. The barrier layer comprises at least one barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one component of oxygen, nitrogen or carbon. A ratio of the component to the barrier material is not less than about 0.45. The fabrication method of the barrier layer applies a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr substantially without forming crystalline material therein.

    摘要翻译： 公开了阻挡层及其制造。 阻挡层包含选自Ta，W，Ti，Ru，Zr，Hf，V，Nb，Cr和Mo中的至少一种阻挡材料和氧，氮或碳的至少一种成分。 组分与阻隔材料的比例不小于约0.45。 阻挡层的制造方法施加用于形成阻挡层的工作压力，大约0.5mTorr至大约200mTorr，基本上不形成结晶材料。

    Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology
    35.
    发明申请
    Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology 有权
    通过用于深亚微米半导体技术的原子层沉积来制造包含金属和氮的接触互连层的方法

    公开(公告)号：US20050054196A1

    公开(公告)日：2005-03-10

    申请号：US10657505

    申请日：2003-09-08

    申请人： Chii-Ming Wu ,  Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    发明人： Chii-Ming Wu ,  Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/8249

    CPC分类号： H01L21/76877 ,  H01L21/28562 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrate. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)2}4 avoids halide contamination from a titanium halide precursor and is safer to handle than a titanium nitrate. After a monolayer of the titanium precursor is deposited on a substrate, a nitrogen containing reactant is introduced to form a TiN monolayer which is followed by a second purge. For TiSiN, a silicon source gas is fed into the process chamber after the TiN monolayer formation. The process is repeated several times to produce a composite layer comprised of a plurality of monolayers that fills a contact hole. The ALD method is cost effective and affords an interconnect with lower impurity levels and better step coverage than conventional PECVD or CVD processes.

    摘要翻译： 使用原子层沉积方法在衬底上沉积厚度约为50nm或更小的TiN或TiSiN膜。 四（二甲基氨基）钛（TDMAT），四（二乙基酰氨基）钛（TDEAT）或Ti {OCH（CH 3）2} 4）的钛前体避免了卤化钛前体的卤化物污染，并且比硝酸钛更安全 。 将钛前体的单层沉积在基底上之后，引入含氮反应物以形成TiN单层，随后进行第二次吹扫。 对于TiSiN，在TiN单层形成之后，将硅源气体进料到处理室中。 该过程重复几次以产生由填充接触孔的多个单层组成的复合层。 ALD方法具有成本效益，并且提供了比常规PECVD或CVD工艺更低的杂质水平和更好的阶梯覆盖的互连。

    Methods for Via Structure with Improved Reliability
    36.
    发明申请
    Methods for Via Structure with Improved Reliability 有权
    通过结构改进可靠性的方法

    公开(公告)号：US20120322261A1

    公开(公告)日：2012-12-20

    申请号：US13595835

    申请日：2012-08-27

    申请人： Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

    发明人： Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

    IPC分类号： H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods for forming a via structure are provided. The method includes depositing a first-layer conductive line over a semiconductor substrate, forming a dielectric layer over the first-layer conductive line, forming a via opening in the dielectric layer and exposing the first-layer conductive line in the via opening, forming a recess portion in the first-layer conductive line, and filling the via opening to form a via extending through the dielectric layer to the first-layer conductive line. The via has a substantially tapered profile and substantially extends into the recess in the first-layer conductive line.

    摘要翻译： 提供了形成通孔结构的方法。 该方法包括在半导体衬底上沉积第一层导电线，在第一层导电线上形成电介质层，在电介质层中形成通孔，并在通路孔中露出第一层导电线，形成 在第一层导电线中的凹陷部分，并且填充通孔开口以形成延伸通过介电层到第一层导电线的通孔。 通孔具有基本上锥形的轮廓并且基本上延伸到第一层导电线中的凹部中。

    Barrier Material and Process for Cu Interconnect
    38.
    发明申请
    Barrier Material and Process for Cu Interconnect 有权
    铜互连的阻挡材料和工艺

    公开(公告)号：US20080280432A1

    公开(公告)日：2008-11-13

    申请号：US12181770

    申请日：2008-07-29

    申请人： Chung-Liang Chang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    发明人： Chung-Liang Chang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76846 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods.

    摘要翻译： 描述了半导体扩散阻挡层及其制造方法。 阻挡层包括至少一层TaN，TiN，WN，TbN，VN，ZrN，CrN，WC，WN，WCN，NbN，AlN及其组合。 阻挡层还可以包括富金属表面。 实施例优选包括约10至500埃厚的胶层，由Ru，Ta，Ti，W，Co，Ni，Al，Nb，AlCu和富含金属的氮化物组成的胶层及其组合。 胶层厚度与阻挡层厚度的比率优选为约1〜50。其他优选实施方案还包括导体退火步骤。 可以使用PVD，CVD，PECVD，PEALD和/或ALD方法沉积各种层，包括氮化和硅化方法。