公开(公告)号：US07202512B2

公开(公告)日：2007-04-10

申请号：US10915362

申请日：2004-08-11

Applicant: Pang-Shiu Chen ,  Sheng-Wei Lee ,  Kao-Feng Liao ,  Lih-Juann Chen ,  Chee-Wee Liu

Inventor： Pang-Shiu Chen ,  Sheng-Wei Lee ,  Kao-Feng Liao ,  Lih-Juann Chen ,  Chee-Wee Liu

IPC: H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L29/165

Abstract: A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.

Abstract translation: 提供了薄应变松弛SiGe层的结构及其制造方法。 该结构包括半导体衬底，形成在半导体衬底上的SiGe缓冲层，形成在SiGe缓冲层上的Si（C）层和形成在Si（C）层上的松弛SiGe外延层）。 Si（C）层用于改变形成在Si（C）层上的弛豫SiGe外延层的应变松弛机理。 因此，具有低穿透位错密度，光滑表面的薄弛豫SiGe外延层是可用的。 制造应变松弛SiGe层的制造时间大大降低，表面粗糙度也得到改善。

公开(公告)号：US20060255331A1

公开(公告)日：2006-11-16

申请号：US11489470

申请日：2006-07-20

Applicant: Pang-Shiu Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

Inventor： Pang-Shiu Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

IPC: H01L31/00

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02532

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

Abstract translation: 公开了一种用于在衬底上生长具有多个Ge量子点（QD）的应变Si层和松弛SiGe层的方法。 该方法可以减少穿透位错密度，降低应变硅的表面粗糙度，并进一步缩短形成外延层的生长时间，而不是常规方法。 该方法包括以下步骤：提供硅衬底，形成多个Ge量子点层; 形成一层松弛的Si x 1-x x; 并在亚序列中形成应变硅层; 其中x大于0且小于1。

公开(公告)号：US20050258460A1

公开(公告)日：2005-11-24

申请号：US10909403

申请日：2004-08-03

Applicant: Min-Hung Lee ,  Cheng-Yeh Yu ,  Shing-Chii Lu ,  Chee-Wee Liu

Inventor： Min-Hung Lee ,  Cheng-Yeh Yu ,  Shing-Chii Lu ,  Chee-Wee Liu

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/84 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/938

Abstract: Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the method are also provided.

Abstract translation: 通过离子注入制备压应变硅的制备方法。 将离子注入到含硅衬底中，并且高温处理将离子包含区域的附近转变成应变硅。 还提供了通过该方法制造的晶体管。

公开(公告)号：US20050051861A1

公开(公告)日：2005-03-10

申请号：US10720117

申请日：2003-11-25

Applicant: Jin-Wei Shi ,  Chee-Wee Liu

Inventor： Jin-Wei Shi ,  Chee-Wee Liu

IPC: H01L31/08 ,  H01L31/107

CPC classification number: B82Y10/00 ,  H01L31/107

Abstract: An avalanche photo-detector (APD) is disclosed, which can reduce device capacitance, operating voltage, carrier transport time and dark current as well as increasing response speed and output power. Thus, an avalanche photo-detector (APD) with high saturation power, high gain-bandwidth product, low noise, fast response, low dark current is achieved. The APD includes an absorption layer with graded doping for converting an incident light into carriers, an undoped multiplication layer for multiplying current by means of receiving carriers, a doped field buffer layer sandwiched between the absorption layer and the multiplication layer for concentrating an electric field in the multiplication layer when a bias voltage is applied, and an undoped drift layer sandwiched between the absorption layer and the field buffer layer for capacitance reduction.

公开(公告)号：US06812729B2

公开(公告)日：2004-11-02

申请号：US10175720

申请日：2002-06-19

Applicant: Miin-Jang Chen ,  Ching-Fuh Lin ,  Chee-Wee Liu ,  Min-Hung Lee ,  Shu-Tong Chang

Inventor： Miin-Jang Chen ,  Ching-Fuh Lin ,  Chee-Wee Liu ,  Min-Hung Lee ,  Shu-Tong Chang

IPC: G01R3126

CPC classification number: G01R31/311 ,  G01R31/2656

Abstract: A method for characterizing the quality of the interface between a silicon and a gate insulator in a MOS device includes the steps of: applying at least one current to the MOS device through the gate; detecting at least one electroluminescent signal corresponding to the silicon bandgap energy after the current flows through the MOS device; and outputting the electroluminescent waveform in the time domain. The quality of the interface between a silicon and a gate insulator in the MOS device is determined by analyzing the minority carrier lifetime in silicon. The invention also discloses a characterization system for implementing the method.

Abstract translation: 用于表征MOS器件中的硅和栅极绝缘体之间的界面的质量的方法包括以下步骤：通过栅极将至少一个电流施加到MOS器件; 在电流流过MOS器件之后检测至少一个对应于硅带隙能量的电致发光信号; 并在时域中输出电致发光波形。 通过分析硅中的少数载流子寿命来确定MOS器件中的硅和栅极绝缘体之间的界面的质量。 本发明还公开了一种用于实现该方法的表征系统。

公开(公告)号：US06794309B2

公开(公告)日：2004-09-21

申请号：US10122572

申请日：2002-04-15

Applicant: Chee-Wee Liu ,  Fon Yuan ,  Chung-Hsun Lin

Inventor： Chee-Wee Liu ,  Fon Yuan ,  Chung-Hsun Lin

IPC: H01L2131

CPC classification number: H01L21/02299 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02258 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/30604 ,  H01L21/3144 ,  H01L21/316 ,  H01L21/3185 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/518

Abstract: A method for utilizing a rough insulator to enhance metal-insulator-semiconductor reliability is provided. The method includes steps of: (a) providing a semiconductor substrate; (b) prebaking the semiconductor substrate under a relatively high vacuum to form a rough surface on the semiconductor substrate; and (c) growing an insulator on the semiconductor substrate to form a rough insulator and increase the metal-insulator-semiconductor reliability when the insulator is applied.

Abstract translation: 提供了一种利用粗糙绝缘体来增强金属 - 绝缘体 - 半导体可靠性的方法。 该方法包括以下步骤：（a）提供半导体衬底; （b）在相对高的真空下预烘烤半导体衬底以在半导体衬底上形成粗糙表面; 和（c）在半导体衬底上生长绝缘体以形成粗糙的绝缘体，并且当施加绝缘体时增加金属 - 绝缘体 - 半导体的可靠性。