公开(公告)号：US08364736B2

公开(公告)日：2013-01-29

申请号：US12325516

申请日：2008-12-01

申请人： Chen-Yi Lee ,  Chen-Fong Hsiao ,  Yuan Chen

发明人： Chen-Yi Lee ,  Chen-Fong Hsiao ,  Yuan Chen

IPC分类号： G06F17/14

CPC分类号： G06F17/142

摘要： For a large size FFT computation, this invention decomposes it into several smaller sizes FFT by decomposition equation and then transform the original index from one dimension into multi-dimension vector. By controlling the index vector, this invention could distribute the input data into different memory banks such that both the in-place policy for computation and the multi-bank memory for high-radix structure could be supported simultaneously without memory conflict. Besides, in order to keep memory conflict-free when the in-place policy is also adopted for I/O data, this invention reverses the decompose order of FFT to satisfy the vector reverse behavior. This invention can minimize the area and reduce the necessary clock rate effectively for general sized memory-based FFT processor design.

摘要翻译： 对于大尺寸FFT计算，本发明通过分解方程将其分解成若干较小尺寸的FFT，然后将原始索引从一维变换为多维向量。 通过控制索引向量，本发明可以将输入数据分配到不同的存储体中，使得可以在没有存储器冲突的情况下同时支持用于计算的就地策略和用于高基数结构的多存储存储器。 此外，为了在I / O数据也采用就地策略时保持内存无冲突的冲突，本发明反转FFT的分解顺序以满足向量反向行为。 本发明可以将面积最小化并有效地降低必要的时钟速率，用于一般尺寸的基于存储器的FFT处理器设计。

公开(公告)号：US20120025313A1

公开(公告)日：2012-02-02

申请号：US13272994

申请日：2011-10-13

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L27/12 ,  H01L29/02

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US08048723B2

公开(公告)日：2011-11-01

申请号：US12329279

申请日：2008-12-05

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L21/332

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US20100169402A1

公开(公告)日：2010-07-01

申请号：US12400794

申请日：2009-03-10

申请人： Hung-Lin Chen ,  Yu-Min Lin ,  Dar-Zu Hsu ,  Yuan Chen ,  Chen-Yi Lee

发明人： Hung-Lin Chen ,  Yu-Min Lin ,  Dar-Zu Hsu ,  Yuan Chen ,  Chen-Yi Lee

IPC分类号： G06F17/14

CPC分类号： G06F17/142

摘要： An FFT processor is disclosed, which includes a first multi-pipelined MDC unit, a second multi-pipelined MDC unit and a switching network. The first multi-pipelined MDC unit and the second multi-pipelined MDC unit respectively employ a plurality of MDC circuits to change the positions of the delayers thereof in parallel way. By changing the operation time sequence of the signals in the first multi-pipelined MDC unit and the second multi-pipelined MDC unit, the first multi-pipelined MDC unit is able to directly send the operation results to the second multi-pipelined MDC unit through the switching network.

摘要翻译： 公开了一种FFT处理器，其包括第一多流水线MDC单元，第二多流水线MDC单元和交换网络。 第一多流水线MDC单元和第二多流水线MDC单元分别采用多个MDC电路以并行方式改变其延迟器的位置。 通过改变第一多流水线MDC单元和第二多流水线MDC单元中的信号的操作时间顺序，第一多流水线MDC单元能够直接将操作结果发送到第二多流水线MDC单元 交换网络。

公开(公告)号：US07724772B2

公开(公告)日：2010-05-25

申请号：US11802028

申请日：2007-05-18

申请人： Chen-Yi Lee ,  Chih-Hao Liu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

发明人： Chen-Yi Lee ,  Chih-Hao Liu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

IPC分类号： H04J3/16

CPC分类号： H04L1/0052 ,  H03M13/116 ,  H03M13/6502 ,  H03M13/6519 ,  H03M13/6527 ,  H03M13/6544 ,  H04L2001/0097

摘要： A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive source data possessing real coding dimension and covert it to converted data possessing tolerable coding dimension; judgment bit is set in the converted data to designate the data as source data or not. Later on, shift circuit is used to shift the converted data in certain amount so as to generate a shifted data; meanwhile, the lowest bit and highest bit of shifted data are used to start acquiring real coding dimension to be used respectively as a first data and a second data, or by changing the pattern of acquiring the first data, then the highest bit minus the real coding dimension bit as the starting bit of the first data, and acquiring the real coding dimension from the side of the lowest bit. Finally, a comparison and selection circuit is used to compare the corresponding judgment bit in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.

摘要翻译： 一种用于在通信系统中切换数据的方法和装置，其主要包括：转换电路，用于接收具有实际编码维度的源数据，并将其转换为具有可容忍编码维度的转换数据; 在转换的数据中设置判断位以将数据指定为源数据。 稍后，使用移位电路将转换后的数据移动到一定量，以产生移位数据; 同时，移位数据的最低位和最高位被用于开始获取要被分别用作第一数据和第二数据的实数编码维度，或通过改变获取第一数据的模式，然后最高位减去实数 编码维度位作为第一数据的起始位，并且从最低位的侧面获取实际编码维度。 最后，比较和选择电路用于比较第一和第二数据中相应的判断位，并输出输出数据，其中输出数据是具有上述移位量的源数据。

公开(公告)号：US07724770B2

公开(公告)日：2010-05-25

申请号：US11708608

申请日：2007-02-21

申请人： Chen-Yi Lee ,  Jr-Hau Lu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

发明人： Chen-Yi Lee ,  Jr-Hau Lu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

IPC分类号： H04J3/16

CPC分类号： H04L12/4625

摘要： A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive the source data possessing in a real coding dimension and covert it to converted the data possessing in a tolerable coding dimension; the judgment bits are set in the converted data to designate the data as source data or not. Later on, shifter circuit is used to shift the converted data in certain amount and generates a shifted data; meanwhile, the right side and left side of shifted data are used to start acquiring the real coding dimension to be used respectively as a first data and a second data. Finally, a comparison and selection circuit is used to compare the corresponding judgment bits in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.

摘要翻译： 一种用于在通信系统中切换数据的方法和装置，主要包括一个转换电路，用于接收具有实际编码维度的源数据，并将其转换成可转换的数据，该数据具有可容忍的编码维度; 在转换的数据中设置判断位以将数据指定为源数据。 稍后，使用移位电路将转换的数据移位一定量并产生移位的数据; 同时，使用移位数据的右侧和左侧开始获取要被分别用作第一数据和第二数据的实际编码维度。 最后，比较和选择电路用于比较第一和第二数据中相应的判断位，并输出输出数据，其中输出数据是具有上述移位量的源数据。

公开(公告)号：US08957477B2

公开(公告)日：2015-02-17

申请号：US13272994

申请日：2011-10-13

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US20130111304A1

公开(公告)日：2013-05-02

申请号：US13609829

申请日：2012-09-11

申请人： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

发明人： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

IPC分类号： H03M13/07 ,  G06F11/10

CPC分类号： H03M13/152 ,  H03M13/1525 ,  H03M13/159 ,  H03M13/451 ,  H03M13/6502

摘要： In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to theELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.

摘要翻译： 在循环码解码方法中，解码器分析接收的码字以识别码字中的不可靠符号，并相应地设置候选综合征模式。 然后，校正子计算器计算与候选校正子模式中的一个相关联的评估校正子值，并且错误位置多项式（ELP）生成器根据校正子值生成ELP。 当ELP的程度不大于阈值时，错误校正装置根据ELP校正码字中的错误，并且校正子计算器调整校正子值，并且ELP生成器根据校正的校正子值生成另一ELP， 除此以外。

公开(公告)号：US08263462B2

公开(公告)日：2012-09-11

申请号：US12347123

申请日：2008-12-31

申请人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L29/772

CPC分类号： H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

摘要翻译： 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。

公开(公告)号：US20110273239A1

公开(公告)日：2011-11-10

申请号：US12805572

申请日：2010-08-06

申请人： Chen-Yi Lee

发明人： Chen-Yi Lee

IPC分类号： H03B5/12 ,  H03K3/354

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1218 ,  H03B5/1221 ,  H03B5/124 ,  H03B2200/0008

摘要： A dual positive-feedbacks voltage controlled oscillator includes an oscillation circuit and a cross coupled pair circuit. The oscillation circuit includes a first transistor, a second transistor, an inductor and a plurality of capacitors. The gates of the first and second transistors are opposite to each other and coupled to two points of the inductor. The inductor and the capacitors are formed as a LC tank. The cross coupled pair circuit includes a third transistor and a fourth transistor. The gates of the third and fourth transistors are cross coupled to two points of the inductor. Thereby, the gate of the third transistor is coupled to the gate of the second transistor; the gate of the fourth transistor is coupled to the gate of the first transistor; the drain of the third transistor is coupled to the source of the first transistor; and the drain of the fourth transistor is coupled to the source of the second transistor.

摘要翻译： 双正压电压振荡器包括振荡电路和交叉耦合对电路。 振荡电路包括第一晶体管，第二晶体管，电感器和多个电容器。 第一和第二晶体管的栅极彼此相对并耦合到电感器的两个点。 电感器和电容器形成为LC箱。 交叉耦合对电路包括第三晶体管和第四晶体管。 第三和第四晶体管的栅极交叉耦合到电感器的两个点。 由此，第三晶体管的栅极耦合到第二晶体管的栅极; 第四晶体管的栅极耦合到第一晶体管的栅极; 第三晶体管的漏极耦合到第一晶体管的源极; 并且第四晶体管的漏极耦合到第二晶体管的源极。