公开(公告)号：US08384414B2

公开(公告)日：2013-02-26

申请号：US13031748

申请日：2011-02-22

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H03K19/00

CPC分类号： G06F21/556

摘要： A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected.

摘要翻译： 一种用于在不确定时间实现黑客检测和阻止功能的方法和电路，以及设置有被摄体电路所在的设计结构。 一个电路包括一个围绕要保护的电路内的动态总线的天线。 天线与动态总线节点一起被设计成平均总线访问激活连接到电容器的场效应晶体管（FET）。 FET通过天线在指定数量的激活中排出电容器。 电容器具有到电压供应轨VDD的泄漏路径，该电压供应轨VDD在动态总线静止的时间（如10到100个周期）之后将电容器充电回来。 电容器提供黑客检测信号，以便响应于确定动态总线比功能预期更有活力来暂时阻止要被保护的电路的操作。

公开(公告)号：US20110298052A1

公开(公告)日：2011-12-08

申请号：US12793118

申请日：2010-06-03

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Kelly L. Williams

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0688 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/1203

摘要： A vertical structure is formed upon a semiconductor substrate. The vertical structure comprises four dielectric layers parallel to a top surface of the semiconductor substrate and three conducting layers, one conducting layer between each vertically adjacent dielectric layer. A first FET (field effect transistor) and a third FET are arranged parallel to the top surface of the semiconductor and a second FET is arranged orthogonal to the top surface of the semiconductor. All three FETs are independently controllable. The first conducting layer is a gate electrode of the first FET; the second conducting layer is a gate electrode of the second FET, and the third conducting layer is the gate electrode of the third FET.

摘要翻译： 在半导体衬底上形成垂直结构。 垂直结构包括平行于半导体衬底的顶表面的四个电介质层和三个导电层，每个垂直相邻的电介质层之间的一个导电层。 第一FET（场效应晶体管）和第三FET平行于半导体的顶表面布置，并且第二FET布置成与半导体的顶表面正交。 所有三个FET均可独立控制。 第一导电层是第一FET的栅电极; 第二导电层是第二FET的栅电极，第三导电层是第三FET的栅电极。

公开(公告)号：US20100308413A1

公开(公告)日：2010-12-09

申请号：US12478098

申请日：2009-06-04

申请人： Phil Christopher Felice Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Kelly L. Williams

发明人： Phil Christopher Felice Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Kelly L. Williams

IPC分类号： H01L27/06 ,  H01L21/8238 ,  G06F17/50

CPC分类号： H01L27/092 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0688

摘要： A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

摘要翻译： 具有单个栅电极的3-D（三维）逆变器。 单栅电极在栅电极和第一掺杂类型的第一FET（场效应晶体管）的主体之间具有第一栅极电介质，第一FET在半导体衬底中具有第一源/漏区，或在第 半导体衬底。 单栅电极在栅电极和与第一FET相反掺杂的第二FET的本体之间具有第二栅极电介质。 第二FET的第二源极/漏极区域由在第一源极/漏极区域上生长的外延层形成。

公开(公告)号：US07541829B1

公开(公告)日：2009-06-02

申请号：US12131487

申请日：2008-06-02

申请人： Ronald J. Bolam ,  Terrance W. Kueper ,  David P. Paulsen ,  John E. Sheets, II

发明人： Ronald J. Bolam ,  Terrance W. Kueper ,  David P. Paulsen ,  John E. Sheets, II

IPC分类号： G01R31/00

CPC分类号： G01R31/2879

摘要： A method for correcting of asymmetric shifts in threshold voltage of transistors caused by effects such as negative-bias temperature instability (NBTI) during burn-in. The method may include providing logic patterns to an integrated circuit, such that devices that were stressed during burn-in are relaxed, and devices that suffered less stress during burn-in are stressed.

摘要翻译： 用于校正由老化期间的负偏压温度不稳定性（NBTI）等效应引起的晶体管阈值电压的非对称偏移的方法。 该方法可以包括向集成电路提供逻辑图案，使得在老化期间受到压力的装置被放宽，并且在老化期间遭受较少应力的装置受到压力。

公开(公告)号：US20130341720A1

公开(公告)日：2013-12-26

申请号：US13533484

申请日：2012-06-26

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L29/78 ,  G06F17/50 ,  H01L21/336

CPC分类号： H01L29/4238 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7831 ,  H01L29/7848

摘要： A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage.

摘要翻译： 一种用于利用替换金属栅极处理（RMGP）来实现在栅极内具有栅极的场效应晶体管（FET）的方法和电路，以及设置有该电路所在的设计结构。 利用RMGP的场效应晶体管包括在衬底上的介电层上的大致中心的金属栅极区域中的牺牲栅极，在衬底中形成的源极和漏极，一对电介质间隔物，第一金属栅极和第二金属栅极 替换中心金属栅极区域内的牺牲栅极，以及分离第一金属栅极和第二金属栅极的第二栅极介电层。 在中心金属栅极区域的相对侧上形成相应的电触点，用于将第一金属栅极和第二金属栅极电连接到相应的电压。

公开(公告)号：US20130313441A1

公开(公告)日：2013-11-28

申请号：US13478821

申请日：2012-05-23

申请人： Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： G01T1/17

CPC分类号： G01T1/247

摘要： An apparatus includes a first radiation detector to generate a first signal when a first radiation level is exceeded and a second radiation detector to generate a second signal when a second radiation level is exceeded. The second radiation level is greater than the first radiation level. A first circuit is susceptible to soft errors at the first radiation level and a second circuit is susceptible to soft errors at the second radiation level. A control unit may suspend use of the first circuit and activate use of the second circuit if the first signal is received and the second signal is not received. The first and second circuits may be memory cells or logic circuits.

摘要翻译： 一种装置包括：当超过第一辐射水平时产生第一信号的第一辐射检测器和当超过第二辐射水平时产生第二信号的第二辐射检测器。 第二辐射水平大于第一辐射水平。 第一电路易受第一辐射电平处的软错误的影响，第二电路易受第二辐射电平处的软错误的影响。 如果接收到第一信号并且没有接收到第二信号，则控制单元可以暂停使用第一电路并激活第二电路的使用。 第一和第二电路可以是存储器单元或逻辑电路。

公开(公告)号：US08492903B2

公开(公告)日：2013-07-23

申请号：US13171919

申请日：2011-06-29

申请人： Gerald K. Bartley ,  Philip R. Germann ,  David P. Paulsen ,  John E. Sheets, II

发明人： Gerald K. Bartley ,  Philip R. Germann ,  David P. Paulsen ,  John E. Sheets, II

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06544

摘要： A system comprises a first integrated circuit (IC) chip that includes a first electronic component; a second IC chip that includes a second electronic component; a through silicon via (TSV) in the second IC chip that electrically couples the first electronic component to the second electronic component; and a signal gating transistor that fully occludes the TSV.

摘要翻译： 一种系统包括：第一集成电路（IC）芯片，其包括第一电子部件; 包括第二电子部件的第二IC芯片; 在所述第二IC芯片中的通过硅通孔（TSV）将所述第一电子部件电耦合到所述第二电子部件; 以及完全封闭TSV的信号门控晶体管。

公开(公告)号：US08456187B2

公开(公告)日：2013-06-04

申请号：US13091243

申请日：2011-04-21

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H03K19/00

CPC分类号： H01L21/761 ,  H01L21/76283

摘要： A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail.

摘要翻译： 一种用于通过调制定时敏感电路的阈值电压偏移来在诸如集成电路或芯片上的系统（SOC）的半导体芯片的不确定时间来实现临时禁用功能的方法和电路，以及 提供了主题电路所在的设计结构。 时序敏感电路设计为对阈值电压偏移敏感，并置于独立的电压控制硅区域上。 启动时，独立的电压控制硅区域接地，然后悬空。 每次检测到黑客尝试或预定义的功能奇偶性时，将电荷施加到独立的受控硅区域。 在定义的电荷累积之后，对独立电压控制的硅​​区域之上的定时敏感电路中的器件阈值电压进行调制，使定时敏感电路失效。

公开(公告)号：US20120268160A1

公开(公告)日：2012-10-25

申请号：US13091243

申请日：2011-04-21

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H02H5/00 ,  H01L21/762

CPC分类号： H01L21/761 ,  H01L21/76283

摘要： A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail.

摘要翻译： 一种用于通过调制定时敏感电路的阈值电压偏移来在诸如集成电路或芯片上的系统（SOC）的半导体芯片的不确定时间来实现临时禁用功能的方法和电路，以及 提供了主题电路所在的设计结构。 时序敏感电路设计为对阈值电压偏移敏感，并置于独立的电压控制硅区域上。 启动时，独立的电压控制硅区域接地，然后悬空。 每次检测到黑客尝试或预定义的功能奇偶性时，将电荷施加到独立的受控硅区域。 在定义的电荷累积之后，对独立电压控制的硅​​区域之上的定时敏感电路中的器件阈值电压进行调制，使定时敏感电路失效。

公开(公告)号：US20120216301A1

公开(公告)日：2012-08-23

申请号：US13031748

申请日：2011-02-22

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： G06F11/00

CPC分类号： G06F21/556

摘要： A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected.

摘要翻译： 一种用于在不确定时间实现黑客检测和阻止功能的方法和电路，以及设置有被摄体电路所在的设计结构。 一个电路包括一个围绕要保护的电路内的动态总线的天线。 天线与动态总线节点一起被设计成平均总线访问激活连接到电容器的场效应晶体管（FET）。 FET通过天线在指定数量的激活中排出电容器。 电容器具有到电压供应轨VDD的泄漏路径，该电压供应轨VDD在动态总线静止的时间（如10到100个周期）之后将电容器充电回来。 电容器提供黑客检测信号，以便响应于确定动态总线比功能预期更有活力来暂时阻止要被保护的电路的操作。