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公开(公告)号：US08492903B2
公开(公告)日：2013-07-23
申请号：US13171919
申请日：2011-06-29
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06544
摘要： A system comprises a first integrated circuit (IC) chip that includes a first electronic component; a second IC chip that includes a second electronic component; a through silicon via (TSV) in the second IC chip that electrically couples the first electronic component to the second electronic component; and a signal gating transistor that fully occludes the TSV.
摘要翻译： 一种系统包括：第一集成电路（IC）芯片，其包括第一电子部件; 包括第二电子部件的第二IC芯片; 在所述第二IC芯片中的通过硅通孔（TSV）将所述第一电子部件电耦合到所述第二电子部件; 以及完全封闭TSV的信号门控晶体管。
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2.发明申请Implementing Semiconductor Signal-Capable Capacitors with Deep Trench and TSV Technologies 失效采用深沟槽和TSV技术实现半导体信号电容公开(公告)号：US20130277798A1
公开(公告)日：2013-10-24
申请号：US13449480
申请日：2012-04-18
CPC分类号： H01L29/945 , H01L29/66181
摘要： A method and structures are provided for implementing semiconductor signal-capable capacitors with deep trench and Through-Silicon-Via (TSV) technologies. A deep trench N-well structure is formed and an implant is provided in the deep trench N-well structure with a TSV formed in a semiconductor chip. At least one angled implant is created around the TSV in a semiconductor chip. The TSV is surrounded with a dielectric layer and filled with a conducting material which forms one electrode of the capacitor. A connection is made to one implant forming a second electrode to the capacitor.
摘要翻译： 提供了一种用于实现具有深沟槽和透硅（Via-Silicon-Via，TSV）技术的具有半导体信号能力的电容器的方法和结构。 形成深沟槽N阱结构，并且在深沟槽N阱结构中提供植入物，其中TSV形成在半导体芯片中。 在半导体芯片中的TSV周围形成至少一个成角度的植入物。 TSV被介电层包围并填充有形成电容器的一个电极的导电材料。 连接到形成到电容器的第二电极的一个注入件。
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3.发明申请Power Domain Controller With Gated Through Silicon Via Having FET With Horizontal Channel 失效带栅极通孔的电源域控制器通过具有水平通道的FET公开(公告)号：US20120146711A1
公开(公告)日：2012-06-14
申请号：US12966303
申请日：2010-12-13
IPC分类号： G11C5/14 , H01L21/336 , H01L29/78
CPC分类号： H01L27/088 , H01L21/823431 , H01L21/823437 , H01L23/481 , H01L29/785 , H01L2224/131 , H01L2224/16145 , H01L2924/014
摘要： A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.
摘要翻译： 半导体芯片具有选通硅通孔（TSVG）。 可以切换TSVG，使得TSVG可以导通或不导通。 半导体芯片可以在下位半导体芯片和较高半导体芯片之间使用，以控制下位半导体芯片上的电压供应是连接到上级半导体芯片中的电压域还是与其断开。 TSVG包括由下级芯片作为开关控制的FET。
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公开(公告)号：US20120211829A1
公开(公告)日：2012-08-23
申请号：US13029490
申请日：2011-02-17
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/26586 , H01L24/16 , H01L25/0657 , H01L27/0922 , H01L29/0847 , H01L29/4236 , H01L29/4238 , H01L29/66666 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/00
摘要： A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.
摘要翻译： 场效应晶体管具有栅极，源极和漏极。 栅极具有从半导体芯片基板的一个表面延伸穿过半导体芯片基板的相对表面的通孔。 源极在半导体芯片衬底的一个表面上具有注入在半导体芯片衬底中的第一环状的离子掺杂剂，该半导体芯片衬底围绕通孔的一端。 漏极具有注入在半导体芯片衬底中的第二环形离子掺杂剂，该环状氧化物围绕半导体芯片衬底的相对表面上的通孔的相对端。
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5.发明申请Interdependent Microchip Functionality for Defeating Exploitation Attempts 审中-公开相互依赖的Microchip功能，以打败开发尝试公开(公告)号：US20100026337A1
公开(公告)日：2010-02-04
申请号：US12181376
申请日：2008-07-29
申请人： Gerald K. Bartley , Darryl J. Becker , Paul E. Dahlen , Philip R. Germann , Andrew B. Maki , Mark O. Maxson , John E. Sheets, II
发明人： Gerald K. Bartley , Darryl J. Becker , Paul E. Dahlen , Philip R. Germann , Andrew B. Maki , Mark O. Maxson , John E. Sheets, II
IPC分类号： H03K19/00
CPC分类号： G06F21/75 , G06F21/86 , H01L2224/16145 , H01L2224/16227
摘要： An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon vias or other interconnects.
摘要翻译： 一种集成电路组件，包括与第二堆叠微芯片共享相互依赖功能的微芯片。 微芯片的物理布置或功能的交替可以启动旨在保护与微芯片中的一个相关联的安全敏感电路的防御动作。 微芯片可以使用硅通孔或其他互连进行通信。
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公开(公告)号：US20100026336A1
公开(公告)日：2010-02-04
申请号：US12181367
申请日：2008-07-29
申请人： Gerald K. Bartley , Darryl J. Becker , Paul E. Dahlen , Philip R. Germann , Andrew B. Maki , Mark O. Maxson , John E. Sheets, II
发明人： Gerald K. Bartley , Darryl J. Becker , Paul E. Dahlen , Philip R. Germann , Andrew B. Maki , Mark O. Maxson , John E. Sheets, II
IPC分类号： H03K19/00
CPC分类号： G06F21/86 , G06F21/75 , H01L23/57 , H01L2224/32225
摘要： An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.
摘要翻译： 检测微芯片篡改的集成电路组件和相关联的方法可以包括与导电层电连通的多个连接。 防御性电路可能会阻止微芯片的分析，其中连接不再连接到导电层。 防御性电路可以类似地启动，其中连接不想与导电层电连通的连接是连接的。
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公开(公告)号：US20100025479A1
公开(公告)日：2010-02-04
申请号：US12181401
申请日：2008-07-29
申请人： Gerald K Bartley , Darryl J. Becker , Todd A. Christensen , Paul E. Dahlen , Philip R. Germann , Andrew B. Maki , Mark O. Maxson , John E. Sheets, II
发明人： Gerald K Bartley , Darryl J. Becker , Todd A. Christensen , Paul E. Dahlen , Philip R. Germann , Andrew B. Maki , Mark O. Maxson , John E. Sheets, II
IPC分类号： G06K19/06
CPC分类号： G06F21/87
摘要： A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.
摘要翻译： 一种方法和装置包括掺杂在微芯片内的导电材料，其在离子存在下累积可检测的电荷。 这样的离子可能由聚焦离子束或其他不受欢迎的技术开发而产生。 感测嵌入的掺杂材料中的电荷积累的电路可以启动旨在击败篡改操作的防御动作。
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8.发明授权Power domain controller with gated through silicon via having FET with horizontal channel 失效具有通过硅封装的电源域控制器通过具有水平通道的FET公开(公告)号：US08466024B2
公开(公告)日：2013-06-18
申请号：US12966303
申请日：2010-12-13
IPC分类号： H01L21/336
CPC分类号： H01L27/088 , H01L21/823431 , H01L21/823437 , H01L23/481 , H01L29/785 , H01L2224/131 , H01L2224/16145 , H01L2924/014
摘要： A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.
摘要翻译： 半导体芯片具有选通硅通孔（TSVG）。 可以切换TSVG，使得TSVG可以导通或不导通。 半导体芯片可以在下位半导体芯片和较高半导体芯片之间使用，以控制下位半导体芯片上的电压供应是连接到上级半导体芯片中的电压域还是与其断开。 TSVG包括由下级芯片作为开关控制的FET。
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9.发明授权Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies 失效实现具有深沟槽和TSV技术的半导体信号电容器公开(公告)号：US08642456B2
公开(公告)日：2014-02-04
申请号：US13449480
申请日：2012-04-18
IPC分类号： H01L21/425
CPC分类号： H01L29/945 , H01L29/66181
摘要： A method and structures are provided for implementing semiconductor signal-capable capacitors with deep trench and Through-Silicon-Via (TSV) technologies. A deep trench N-well structure is formed and an implant is provided in the deep trench N-well structure with a TSV formed in a semiconductor chip. At least one angled implant is created around the TSV in a semiconductor chip. The TSV is surrounded with a dielectric layer and filled with a conducting material which forms one electrode of the capacitor. A connection is made to one implant forming a second electrode to the capacitor.
摘要翻译： 提供了一种用于实现具有深沟槽和透硅（Via-Silicon-Via，TSV）技术的具有半导体信号能力的电容器的方法和结构。 形成深沟槽N阱结构，并且在深沟槽N阱结构中提供植入物，其中TSV形成在半导体芯片中。 在半导体芯片中的TSV周围形成至少一个成角度的植入物。 TSV被介电层包围并填充有形成电容器的一个电极的导电材料。 连接到形成到电容器的第二电极的一个注入件。
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公开(公告)号：US08172140B2
公开(公告)日：2012-05-08
申请号：US12181401
申请日：2008-07-29
申请人： Gerald K Bartley , Darryl J. Becker , Todd A. Christensen , Paul E. Dahlen , Philip R. Germann , Andrew B. Maki , Mark O. Maxson , John E. Sheets, II
发明人： Gerald K Bartley , Darryl J. Becker , Todd A. Christensen , Paul E. Dahlen , Philip R. Germann , Andrew B. Maki , Mark O. Maxson , John E. Sheets, II
IPC分类号： G06K7/08
CPC分类号： G06F21/87
摘要： A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.
摘要翻译： 一种方法和装置包括掺杂在微芯片内的导电材料，其在离子存在下累积可检测的电荷。 这样的离子可能由聚焦离子束或其他不受欢迎的技术开发而产生。 感测嵌入的掺杂材料中的电荷积累的电路可以启动旨在击败篡改操作的防御动作。
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