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37 条记录 (耗时 0.024 秒)

    Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors
    31.
    发明授权
    Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors 有权
    制造应变硅晶体管和应变硅CMOS晶体管的方法

    公开(公告)号：US07491615B2

    公开(公告)日：2009-02-17

    申请号：US11162798

    申请日：2005-09-23

    申请人： Chih-Ning Wu ,  Hsin Tai ,  Chung-Ju Lee ,  Wei-Tsun Shiau

    发明人： Chih-Ning Wu ,  Hsin Tai ,  Chung-Ju Lee ,  Wei-Tsun Shiau

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.

    摘要翻译： 制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底在其上包含栅极结构; 执行蚀刻工艺以形成对应于半导体衬底内的栅极结构的两个凹部; 在半导体衬底上进行氧冲洗; 对所述半导体衬底进行清洁处理; 并且在每个用于形成源/漏区的凹槽中执行选择性外延生长（SEG）以形成外延层。

    Metal oxide semiconductor transistor
    32.
    发明授权
    Metal oxide semiconductor transistor 有权
    金属氧化物半导体晶体管

    公开(公告)号：US07214988B2

    公开(公告)日：2007-05-08

    申请号：US11162693

    申请日：2005-09-20

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： H01L29/76

    CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

    摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

    摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

    Etching process compatible with DUV lithography
    33.
    发明申请
    Etching process compatible with DUV lithography 审中-公开
    蚀刻工艺兼容DUV光刻

    公开(公告)号：US20060110688A1

    公开(公告)日：2006-05-25

    申请号：US10993593

    申请日：2004-11-19

    申请人： Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： G03F7/36

    CPC分类号： G03F7/405 ,  G03F7/40

    摘要： An etching process compatible with DUV lithography is described. A mask layer is previously formed over a material layer to be etched through a DUV lithography process of 193 nm or 157 nm. Then, plasma etching is performed to pattern the material layer using the mask layer as an etching mask, wherein the etching gas causes a protective layer to form on the surface of the mask layer. The etching gas of the plasma etching includes at least a halogen-containing gas and Xe, wherein the halogen can be F, Cl, Br or a combination thereof.

    摘要翻译： 描述了与DUV光刻相兼容的蚀刻工艺。 预先通过193nm或157nm的DUV光刻工艺在待蚀刻的材料层上形成掩模层。 然后，进行等离子体蚀刻，使用掩模层作为蚀刻掩模对材料层进行图案化，其中蚀刻气体在掩模层的表面上形成保护层。 等离子体蚀刻的蚀刻气体至少包含含卤素的气体和Xe，其中卤素可以是F，Cl，Br或其组合。

    Self-assembled monolayer for pattern formation
    35.
    发明授权
    Self-assembled monolayer for pattern formation 有权
    自组装单层图案形成

    公开(公告)号：US08883646B2

    公开(公告)日：2014-11-11

    申请号：US13567250

    申请日：2012-08-06

    申请人： Tsung-Min Huang ,  Chung-Ju Lee ,  Chien-Hua Huang

    发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Chien-Hua Huang

    IPC分类号： H01L21/311

    CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

    摘要： The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

    摘要翻译： 本公开涉及制造半导体器件的方法。 在一些实施例中，半导体器件包括图案化表面。 该图案可以由自组装单层形成。 所公开的方法提供可以快速沉积的自组装单层，从而增加生产量和降低成本，以及提供具有基本均匀形状的图案。

    Method of fabricating semiconductor devices and method of removing a spacer
    37.
    发明授权
    Method of fabricating semiconductor devices and method of removing a spacer 有权
    制造半导体器件的方法和去除间隔物的方法

    公开(公告)号：US07338910B2

    公开(公告)日：2008-03-04

    申请号：US11162952

    申请日：2005-09-29

    申请人： Chung-Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

    发明人： Chung-Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/76834 ,  H01L21/28518 ,  H01L21/31111

    摘要： A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on the top or the surface of the semiconductor substrate and the electrode; and removing the spacer by steps of performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant. With respect to another aspect, a method of removing a spacer is also disclosed. The method includes performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant.

    摘要翻译： 公开了制造半导体器件的方法。 该方法包括在半导体衬底上限定电极; 在所述电极的至少一个侧壁上形成间隔物; 在所述半导体衬底上使用所述间隔件作为掩模进行处理操作，并在所述半导体衬底和所述电极的顶部或表面上形成材料层; 并且通过在100℃至150℃的温度范围内进行湿蚀刻工艺的步骤去除间隔物，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。 关于另一方面，还公开了一种去除间隔物的方法。 该方法包括在100℃至150℃范围内的温度下进行湿蚀刻工艺，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。