公开(公告)号：US20140038428A1

公开(公告)日：2014-02-06

申请号：US13567250

申请日：2012-08-06

申请人： Tsung-Min Huang ,  Chung-Ju Lee ,  Chien-Hua Huang

发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Chien-Hua Huang

IPC分类号： H01L21/027

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

摘要： The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

摘要翻译： 本公开涉及制造半导体器件的方法。 在一些实施例中，半导体器件包括图案化表面。 该图案可以由自组装单层形成。 所公开的方法提供可以快速沉积的自组装单层，从而增加生产量和降低成本，以及提供具有基本均匀形状的图案。

公开(公告)号：US09245841B2

公开(公告)日：2016-01-26

申请号：US13553535

申请日：2012-07-19

申请人： Chien-Hua Huang ,  Chung-Ju Lee ,  Tsung-Min Huang

发明人： Chien-Hua Huang ,  Chung-Ju Lee ,  Tsung-Min Huang

IPC分类号： H01L29/08 ,  H01L35/24 ,  H01L51/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/02123 ,  H01L21/31105 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76867 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.

摘要翻译： 提供了一种半导体器件及其制造方法。 半导体器件包括具有一部分反应性材料的基底层; 以及自组装分子与在该部分上形成的反应性材料反应的自组装保护层。

公开(公告)号：US08883646B2

公开(公告)日：2014-11-11

申请号：US13567250

申请日：2012-08-06

申请人： Tsung-Min Huang ,  Chung-Ju Lee ,  Chien-Hua Huang

发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Chien-Hua Huang

IPC分类号： H01L21/311

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

摘要： The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

摘要翻译： 本公开涉及制造半导体器件的方法。 在一些实施例中，半导体器件包括图案化表面。 该图案可以由自组装单层形成。 所公开的方法提供可以快速沉积的自组装单层，从而增加生产量和降低成本，以及提供具有基本均匀形状的图案。

公开(公告)号：US20140065816A1

公开(公告)日：2014-03-06

申请号：US13600504

申请日：2012-08-31

申请人： Tsung-Jung Tsai ,  Hsin-Chieh Yao ,  Chien-Hua Huang ,  Chung-Ju Lee

发明人： Tsung-Jung Tsai ,  Hsin-Chieh Yao ,  Chien-Hua Huang ,  Chung-Ju Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76831

摘要： Among other things, one or more techniques for forming a low k dielectric around a metal line during an integrated circuit (IC) fabrication process are provided. In an embodiment, a metal line is formed prior to forming a surrounding low k dielectric layer around the metal line. In an embodiment, the metal line is formed by filling a trench space in a skeleton layer with metal. In this embodiment, the skeleton layer is removed to form a dielectric space in a different location than the trench space. The dielectric space is then filled with a low k dielectric material to form a surrounding low k dielectric layer around the metal line. In this manner, damage to the surrounding low k dielectric layer, that would otherwise occur if the surrounding low k dielectric layer was etched, for example, is mitigated.

摘要翻译： 其中，提供了在集成电路（IC）制造过程中用于在金属线周围形成低k电介质的一种或多种技术。 在一个实施例中，在围绕金属线形成周围的低k电介质层之前形成金属线。 在一个实施例中，通过用金属填充骨架层中的沟槽空间来形成金属线。 在该实施例中，除去骨架层以在与沟槽空间不同的位置形成电介质空间。 然后用低k电介质材料填充电介质空间，以在金属线周围形成周围的低k电介质层。 以这种方式，例如，如果周围的低k电介质层被蚀刻，则会损坏周围的低k电介质层，否则会被破坏。

公开(公告)号：US10002820B2

公开(公告)日：2018-06-19

申请号：US13478815

申请日：2012-05-23

申请人： Sun-Rong Jan ,  Che-Yu Yeh ,  Chee Wee Liu ,  Chien-Hua Huang ,  Bing J. Sheu

发明人： Sun-Rong Jan ,  Che-Yu Yeh ,  Chee Wee Liu ,  Chien-Hua Huang ,  Bing J. Sheu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

公开(公告)号：US20060232322A1

公开(公告)日：2006-10-19

申请号：US11162667

申请日：2005-09-19

申请人： Chien-Hua Huang

发明人： Chien-Hua Huang

IPC分类号： H03K17/687 ,  H03H11/24 ,  H03K17/296

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： A voltage transfer circuit outputs an equivalent to an input voltage when enabled. Otherwise, the transfer circuit is in standby and outputs an equivalent to a standby voltage (e.g., signal ground). The voltage transfer circuit includes a switching circuit, a standby circuit, and an input-transfer circuit. The output of the transfer circuit is fed back to both the switching circuit and the input-transfer circuit. When the transfer circuit is in standby, the feedback of the output voltage provides for voltage-balancing in the input-transfer circuit, thereby reducing or eliminating leakage current in the input-transfer circuit. Similarly, when the transfer circuit is in active mode, the feedback of the output voltage provides for voltage-balancing in the standby circuit, thereby reducing or eliminating leakage current in the standby circuit.

摘要翻译： 电压传输电路在使能时输出等效于输入电压。 否则，传输电路处于待机状态，并输出等效于待机电压（例如，信号地）。 电压传输电路包括开关电路，备用电路和输入传输电路。 传输电路的输出反馈给开关电路和输入传输电路。 当传送电路处于待机状态时，输出电压的反馈提供输入传输电路中的电压平衡，从而减少或消除输入传输电路中的漏电流。 类似地，当传输电路处于主动模式时，输出电压的反馈提供备用电路中的电压平衡，从而减少或消除备用电路中的漏电流。

公开(公告)号：US20060152990A1

公开(公告)日：2006-07-13

申请号：US11028839

申请日：2005-01-04

申请人： Chien-Hua Huang

发明人： Chien-Hua Huang

IPC分类号： G11C17/18

CPC分类号： G11C11/5692 ,  G11C17/165 ,  G11C17/18 ,  G11C29/02 ,  G11C29/027 ,  G11C29/4401

摘要： A multiple-time electrical fuse programming circuit is described. The circuit includes a programming counter to record the number of programmings, a blowing reference voltage generator to generate a blowing voltage reference wherein the fuse resistance after programming is determined by the blowing voltage reference, at least one self-controlled programmable fuses which includes a programmable fuse and a control circuit. The multiple-time electrical fuse programming circuit also has a fuse detection reference generator and a high voltage power source.

公开(公告)号：US20060150062A1

公开(公告)日：2006-07-06

申请号：US11026354

申请日：2004-12-30

申请人： Chien-Hua Huang

发明人： Chien-Hua Huang

IPC分类号： G11C29/00

CPC分类号： G11C7/1006 ,  G01R31/31816 ,  G06F11/1008 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409

摘要： A method and a system for correcting a soft error in a memory circuit during a stand-by mode are disclosed. According to the disclosure, after reading data from at least one memory cell without outputting the read data through an input/output module of the memory circuit in the stand-by mode, it is determined whether the read data is a soft error. If so, a correct value is written to the memory cell if the read data is the soft error.

摘要翻译： 公开了一种用于在待机模式期间校正存储电路中的软错误的方法和系统。 根据本公开，在从待机模式中经由存储电路的输入/输出模块输出读取数据之后，从至少一个存储单元读取数据之后，确定读取的数据是否为软错误。 如果是这样，如果读取的数据是软错误，则将正确的值写入存储单元。

公开(公告)号：US20060145679A1

公开(公告)日：2006-07-06

申请号：US10905386

申请日：2004-12-30

申请人： Chien-Hua Huang

发明人： Chien-Hua Huang

IPC分类号： G05F3/16 ,  G05F3/20

CPC分类号： G05F3/262 ,  Y10S323/907

摘要： Disclosed herein is a voltage regulator, and related method, for regulating a boost voltage generated by a boost circuit. In one embodiment, the voltage regulator includes a regulated voltage input operable to receive a regulated voltage derived from the boost voltage, a reference voltage input operable to receive a constant reference voltage, and an output node operable to provide a feedback signal to the boost circuit for controlling the generated boost voltage. In addition, the voltage regulator includes at least one transistor coupled to the regulated voltage input, the reference voltage input, and the output node, and operable to produce the feedback signal based on a comparison of the regulated voltage to the reference voltage. The voltage regulator still further includes a variable current source coupled to the output node and having one or more performance characteristics, where the variable current source is operable to generate a variable current at the output node to mitigate the affect of one or more performance characteristics of the at least one transistor based on the comparison and the feedback signal such that the boost circuit generates the boost voltage to be substantially constant.

摘要翻译： 这里公开了一种用于调节由升压电路产生的升压电压的电压调节器和相关方法。 在一个实施例中，电压调节器包括可操作以接收从升压电压导出的调节电压的调节电压输入，可操作以接收恒定参考电压的参考电压输入，以及用于向升压电路提供反馈信号的输出节点 用于控制产生的升压电压。 此外，电压调节器包括耦合到调节电压输入，参考电压输入和输出节点的至少一个晶体管，并且可操作以基于调节电压与参考电压的比较来产生反馈信号。 电压调节器还包括耦合到输出节点并具有一个或多个性能特性的可变电流源，其中可变电流源可操作以在输出节点处产生可变电流，以减轻一个或多个性能特性的影响 基于比较的至少一个晶体管和反馈信号，使得升压电路将升压电压基本上恒定。

公开(公告)号：US07035131B2

公开(公告)日：2006-04-25

申请号：US10840098

申请日：2004-05-06

申请人： Chien-Hua Huang ,  Chung-Cheng Chou

发明人： Chien-Hua Huang ,  Chung-Cheng Chou

IPC分类号： G11C11/24

CPC分类号： G11C29/50016 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/50

摘要： A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corresponding plurality of inactive bit cells of a DRAM; and a current mirror in communication with the common storage node operable to mirror a total leakage current from said plurality of bit cell access transistors when the access transistors are biased to simulate the inactive bit cells.

摘要翻译： 提供了可操作以测量动态随机存取存储器（DRAM）中的泄漏电流的电路，其包括耦合到公共位线，公共字线和公共存储节点的多个DRAM位单元存取晶体管，其中所述存取晶体管可以 被偏置以模拟DRAM的对应的多个非活动位单元; 以及与公共存储节点通信的电流镜，可操作以当存取晶体管被偏置以模拟非活动位单元时，来自所述多个位单元存取晶体管的总泄漏电流。