公开(公告)号：US20110303968A1

公开(公告)日：2011-12-15

申请号：US12813906

申请日：2010-06-11

Applicant: Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Sheng-Chih Lai

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Sheng-Chih Lai

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0483 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines.

Abstract translation: 非易失性存储单元阵列的集成电路在衬底上具有介电堆叠层，并且在介电堆叠层下方的衬底中的注入区域。 电介质堆叠层在平面区域上是连续的，其包括存储非易失性数据的电介质堆叠层的位置，使得这些位置被字线/位线访问。

公开(公告)号：US08072810B2

公开(公告)日：2011-12-06

申请号：US12985743

申请日：2011-01-06

Applicant: Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

Inventor： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

IPC: G11C11/34

CPC classification number: G11C16/0466

Abstract: The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

Abstract translation: 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷俘获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧道法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 使用衬底瞬态热电子注入进行电荷俘获存储器的编程，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。

公开(公告)号：US07881112B2

公开(公告)日：2011-02-01

申请号：US12538582

申请日：2009-08-10

Applicant: Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

Inventor： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

IPC: G11C11/34

CPC classification number: G11C16/0466

Abstract: The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

公开(公告)号：US07863067B2

公开(公告)日：2011-01-04

申请号：US11686108

申请日：2007-03-14

Applicant: Gwo-Yuh Shiau ,  Ming Chyi Liu ,  Tzu-Hsuan Hsu ,  Chia-Shiung Tsai

Inventor： Gwo-Yuh Shiau ,  Ming Chyi Liu ,  Tzu-Hsuan Hsu ,  Chia-Shiung Tsai

IPC: H01L21/00

CPC classification number: H01L21/268 ,  H01L27/1464 ,  H01L27/14683

Abstract: The present disclosure provides a method for fabricating a semiconductor device including providing a semiconductor substrate comprising a first surface and a second surface, wherein at least one imaging sensor is located adjacent the first surface, activating a dopant layer in the semiconductor substrate adjacent the second surface using a localized annealing process, and etching the dopant layer.

Abstract translation: 本公开提供一种制造半导体器件的方法，包括提供包括第一表面和第二表面的半导体衬底，其中至少一个成像传感器位于第一表面附近，激活邻近第二表面的半导体衬底中的掺杂剂层 使用局部退火工艺，并蚀刻掺杂剂层。

公开(公告)号：US20100009504A1

公开(公告)日：2010-01-14

申请号：US12561395

申请日：2009-09-17

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0475 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract translation: 包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。 因此，可以实现非常紧凑，高密度的存储器阵列。 存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。 可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

公开(公告)号：US07387907B2

公开(公告)日：2008-06-17

申请号：US11517296

申请日：2006-09-08

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Yean-Kuen Fang

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Yean-Kuen Fang

IPC: H01L21/00

CPC classification number: H01L27/1462 ,  H01L25/167 ,  H01L27/14625 ,  H01L27/1463 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/15 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An image sensor device and fabrication method thereof wherein a substrate having at least one shallow trench isolation structure therein is provided. At least one photosensor and at least one light emitting element, e.g., such as MOS or LED, are formed in the substrate. The photosensor and the light emitting element are isolated by the shallow trench isolation structure. An opening is formed in the shallow trench isolation structure to expose part of the substrate. An opaque shield is formed in the opening to prevent photons from the light emitting element from striking the photosensor.

Abstract translation: 一种图像传感器装置及其制造方法，其中提供其中具有至少一个浅沟槽隔离结构的基板。 在衬底中形成至少一个光电传感器和至少一个发光元件，例如MOS或LED。 光传感器和发光元件通过浅沟槽隔离结构隔离。 在浅沟槽隔离结构中形成开口以暴露部分衬底。 在开口中形成不透明屏蔽物，以防止来自发光元件的光子撞击光传感器。

公开(公告)号：US20080031039A1

公开(公告)日：2008-02-07

申请号：US11496441

申请日：2006-08-01

Applicant: Tzu-Hsuan Hsu ,  Chao-I Wu ,  Erh-Kun Lai

Inventor： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Erh-Kun Lai

IPC: G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/0483 ,  H01L29/4234 ,  H01L29/7923

Abstract: A method for operating a semiconductor memory device having first and second bit lines, a gate electrode, an insulative layer, and a substrate includes applying first, second, and third biases to the first bit line, the second bit line, and the gate electrode, respectively, to induce carriers from the gate electrode to the insulative layer, where the carriers have the same type of conductivity as majority carriers in the substrate to thereby reduce a threshold voltage of the semiconductor memory device.

Abstract translation: 一种用于操作具有第一和第二位线，栅电极，绝缘层和衬底的半导体存储器件的方法包括将第一，第二和第三偏压施加到第一位线，第二位线和栅电极 分别诱导载流子从栅电极到绝缘层，其中载流子具有与衬底中多数载流子相同的导电性，从而降低半导体存储器件的阈值电压。

公开(公告)号：US20070262354A1

公开(公告)日：2007-11-15

申请号：US11624568

申请日：2007-01-18

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung

IPC: H01L31/113 ,  H01L31/18

CPC classification number: H01L27/14645 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/1464

Abstract: A backside illuminated sensor includes a semiconductor substrate having a front surface and a back surface and a plurality of pixels formed on the front surface of the semiconductor substrate. A dielectric layer is disposed above the front surface of the semiconductor substrate. The sensor further includes a plurality of array regions arranged according to the plurality of pixels. At least two of the array regions have a different radiation response characteristic from each other, such as the first array region having a greater junction depth than the second array region, or the first array region having a greater dopant concentration than the second array region.

Abstract translation: 背面照明传感器包括具有前表面和后表面的半导体衬底以及形成在半导体衬底的前表面上的多个像素。 电介质层设置在半导体衬底的前表面之上。 传感器还包括根据多个像素布置的多个阵列区域。 阵列区域中的至少两个具有彼此不同的辐射响应特性，例如具有比第二阵列区域更大的结深度的第一阵列区域，或者具有比第二阵列区域更大的掺杂剂浓度的第一阵列区域。

公开(公告)号：US20070253258A1

公开(公告)日：2007-11-01

申请号：US11773857

申请日：2007-07-05

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC: G11C11/34

CPC classification number: G11C16/0475

Abstract: A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

Abstract translation: 提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。 当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。 衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口，以消除或减少难以 随后的编程和擦除周期中的擦除条件。

公开(公告)号：US07253458B2

公开(公告)日：2007-08-07

申请号：US10980959

申请日：2004-11-04

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Wen-De Wang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Wen-De Wang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

IPC: H01L27/148

CPC classification number: H01L27/14643 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636

Abstract: A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 μm. At least one dielectric layer is disposed on the substrate covering the pixel. A color filter is disposed on the least one dielectric layer. A microlens array is disposed on the color filter of the pixel, and the sum of the thickness of all dielectric layers and the color filter divided by the pixel width is equal to or less than approximately 1.87.

Abstract translation: 互补金属氧化物半导体场效应晶体管（CMOS-FET）图像传感器。 在基板上形成有源感光像素。 像素的至少一侧具有等于或小于约3μm的宽度。 在覆盖像素的基板上设置至少一个电介质层。 滤色器设置在至少一个电介质层上。 微透镜阵列设置在像素的滤色器上，所有电介质层和滤色器的厚度之和除以像素宽度等于或小于约1.87。