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51 条记录 (耗时 0.045 秒)

    Floating-gate semiconductor structures
    32.
    发明申请
    Floating-gate semiconductor structures 失效

    公开(公告)号：US20050104118A1

    公开(公告)日：2005-05-19

    申请号：US10915107

    申请日：2004-08-09

    申请人： Christopher Diorio ,  Todd Humes

    发明人： Christopher Diorio ,  Todd Humes

    IPC分类号： G11C11/54 ,  G11C11/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883 ,  H01L29/7885

    摘要： Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.

    PMOS memory cell
    33.
    发明申请
    PMOS memory cell 审中-公开
    PMOS存储单元

    公开(公告)号：US20050030827A1

    公开(公告)日：2005-02-10

    申请号：US10936283

    申请日：2004-09-07

    申请人： Troy Gilliland ,  Chad Lindhorst ,  Christopher Diorio ,  Todd Humes ,  Shailendra Srinivas

    发明人： Troy Gilliland ,  Chad Lindhorst ,  Christopher Diorio ,  Todd Humes ,  Shailendra Srinivas

    IPC分类号： G11C16/34 ,  G11C8/02

    CPC分类号： G11C16/3404 ,  G11C16/3468 ,  G11C16/3472 ,  G11C16/3477

    摘要： A single-poly PMOS nonvolatile memory (NVM) cell and a method of programming, erasing and reading such a cell are implemented using a single-poly PMOS NVM cell which includes a floating gate injection transistor, a select switch, and a tunneling capacitor having one plate in common with the floating gate of the injection transistor. Methods of altering the number of electrons on the floating gate of the single-poly PMOS NVM cell are used which, with appropriate biasing of the components permit the power terminals of the cell to have appropriate voltages applied to thereby avoid stuck bits and induce hot electrons onto the floating gate of the NVM cell.

    摘要翻译： 单多晶硅PMOS非易失性存储器（NVM）单元以及编程，擦除和读取这样的单元的方法是使用包括浮置栅极注入晶体管，选择开关和隧穿电容器的单晶体PMOS NVM单元来实现的， 一个板与注入晶体管的浮动栅极共同。 使用改变单多晶硅NMOS NVM单元的浮栅上的电子数量的方法，其中组件的适当偏置允许电池的功率端子施加适当的电压，从而避免卡住位并引起热电子 到NVM单元的浮动栅极上。

    Method and apparatus for programming single-poly pFET-based nonvolatile memory cells
    35.
    发明申请
    Method and apparatus for programming single-poly pFET-based nonvolatile memory cells 有权
    用于编程基于单多晶硅pFET的非易失性存储单元的方法和装置

    公开(公告)号：US20070019476A1

    公开(公告)日：2007-01-25

    申请号：US11528150

    申请日：2006-09-26

    申请人： Christopher Diorio ,  Todd Humes

    发明人： Christopher Diorio ,  Todd Humes

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3468 ,  G11C16/3404 ,  G11C16/3472 ,  G11C16/3477

    摘要： Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection (IHEI). The predetermined event may be, for example, the expiration of a predetermined time period or a determination that a channel has been formed by the BTBT injection process that is sufficiently conducting to support IHEI. Employing BTBT permits a previously overerased or stuck bit to be “unstuck” or “removed” and thus be made usable (i.e., able to be programmed) again.

    摘要翻译： 用于编程基于单多晶硅pFET的非易失性存储单元的方法和装置偏置该单元，从而导致带间隧穿（BTBT），并且由BTBT产生的电子注入到该单元的浮动栅极上。 在预定事件之后，单多晶硅pFET被偏置以引起冲击电离热电子注入（IHEI）。 预定事件可以是例如预定时间段的到期或通过充分进行支持IHEI的BTBT注入处理形成的信道的确定。 使用BTBT允许先前已过度或卡住的位被“解锁”或“移除”，并因此被再次使用（即能够被编程）。

    Adjusting RFID waveform shape in view of detected RF energy
    36.
    发明申请
    Adjusting RFID waveform shape in view of detected RF energy 有权
    鉴于检测到的RF能量调整RFID波形形状

    公开(公告)号：US20060261953A1

    公开(公告)日：2006-11-23

    申请号：US11412170

    申请日：2006-04-25

    申请人： Christopher Diorio ,  Kurt Sundstrom ,  Todd Humes ,  Paul Dietrich

    发明人： Christopher Diorio ,  Kurt Sundstrom ,  Todd Humes ,  Paul Dietrich

    IPC分类号： G08B13/14

    CPC分类号： G06K7/0008

    摘要： Systems, software, devices, and methods are described for an RFID reader system to communicate with RFID tags. RF energy encountered in conjunction with using a selected channel is detected and used to adjust a waveform shaping parameter. RF waves can be transmitted from the reader to the RFID tags and RF waves can be backscattered from the RFID tags. At least some of the RF waves transmitted to or backscattered from the RFID tags have a waveform with a shape according to the adjusted waveform shaping parameter.

    摘要翻译： 描述了RFID读取器系统与RFID标签通信的系统，软件，设备和方法。 检测并结合使用所选择的信道遇到的RF能量来调整波形整形参数。 RF波可以从读取器发送到RFID标签，并且RF波可以从RFID标签反向散射。 从RFID标签发射或反向散射的至少一些RF波具有根据经调整的波形整形参数的形状的波形。

    RFID tags calibrating backscattering period also for non-integer divide ratios
    38.
    发明申请
    RFID tags calibrating backscattering period also for non-integer divide ratios 有权
    RFID标签校准后向散射周期也用于非整数分频比

    公开(公告)号：US20060086810A1

    公开(公告)日：2006-04-27

    申请号：US11258521

    申请日：2005-10-24

    申请人： Christopher Diorio ,  Todd Humes ,  Scott Cooper

    发明人： Christopher Diorio ,  Todd Humes ,  Scott Cooper

    IPC分类号： G06K19/06

    CPC分类号： G06K19/0723

    摘要： An RFID tag that receives a calibration instruction from a reader can determine the basic backscatter period of the symbols to be backscattered. According to some embodiments, when the instruction includes a calibration feature that is to be divided by a divide ratio, the tag measures the duration of the feature in terms of numbers of internal pulses, resulting in a binary L-number. Then at least two versions of the L-number (PR1-number, PR2-number) are combined, so as to yield the effective result of the division alternately, even when the divide ratio is a non-integer. The backscatter period can then be determined from the BP-number and the period of the internal pulses.

    摘要翻译： 从读取器接收校准指令的RFID标签可以确定要反向散射的符号的基本反向散射周期。 根据一些实施例，当指令包括要由分频比除除的校准特征时，标签以内部脉冲数量来测量特征的持续时间，得到二进制L数。 然后组合L个号码（PR 1号，PR 2号码）的至少两个版本，以便即使分频比是非整数也可以交替地产生除法的有效结果。 然后可以根据BP号和内部脉冲的周期来确定反向散射周期。

    Changing manner of determining a query parameter Q used for inventorying RFID tags
    39.
    发明申请
    Changing manner of determining a query parameter Q used for inventorying RFID tags 审中-公开
    更改确定用于清点RFID标签的查询参数Q的方式

    公开(公告)号：US20060071759A1

    公开(公告)日：2006-04-06

    申请号：US11210575

    申请日：2005-08-24

    申请人： Scott Cooper ,  Christopher Diorio ,  Todd Humes ,  Vadim Lobanov

    发明人： Scott Cooper ,  Christopher Diorio ,  Todd Humes ,  Vadim Lobanov

    IPC分类号： H04Q5/22

    CPC分类号： G06K7/0008 ,  G06K7/10029 ,  G06K7/10297 ,  H04Q5/22 ,  H04Q2213/13095

    摘要： RFID system components, such as readers and tags, communicate where the reader inventories a population of tags. The reader evaluates responses from tags by categorizing them in slots. As tags are inventoried, the number of slots based on a Q-parameter is reduced. The reader reduces the Q-parameter first in a first manner, then in a second manner where the second manner is different from the first manner. The first manner and the second manner may be different algorithms, different subroutines of an algorithm, or the same damping algorithm with different damping parameters.

    摘要翻译： 诸如读取器和标签之类的RFID系统组件通信读者清点一批标签的位置。 读者通过在插槽中对它们进行分类来评估标签的响应。 随着标签被盘点，减少了基于Q参数的槽数。 读取器首先以第一种方式降低Q参数，然后以第二种方式与第一种方式不同。 第一种方式和第二种方式可能是不同的算法，算法的不同子程序，或具有不同阻尼参数的相同阻尼算法。