公开(公告)号：US20060011993A1

公开(公告)日：2006-01-19

申请号：US11020702

申请日：2004-12-22

申请人： Joo-Ah Kang ,  June Lee ,  In-Young Kim

发明人： Joo-Ah Kang ,  June Lee ,  In-Young Kim

IPC分类号： H01L29/76

CPC分类号： H01L23/5221 ,  H01L23/522 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of pairs of conductive vias connected to opposite ends of respective ones of the first plurality of conductive junction traces. The first junction block also includes a dummy conductive trace located adjacent the first plurality of conductive junction traces and a pair of dummy conductive vias connected to opposite ends of the dummy junction trace. The integrated circuit device further includes a plurality of upper metallization traces routed on the interlayer insulating layer. The upper metallization traces are configured to electrically connect with the first plurality of pairs of conductive vias and maintain the dummy conductive trace and the pair of dummy conductive vias in an unused and electrically floating condition.

摘要翻译： 集成电路器件包括其上具有层间绝缘层的半导体衬底和嵌入在层间绝缘层中的第一接合块。 第一接合块包括位于层间绝缘层内并排设置的第一多个导电结迹线以及连接到第一多个导电接合迹线中的相应端的相对端的对应的第一多对导电通孔。 第一接合块还包括位于第一多个导电接合迹线附近的虚拟导电迹线和连接到虚拟结迹迹的相对端的一对虚设导电通孔。 集成电路器件还包括在层间绝缘层上布线的多个上部金属化迹线。 上部金属化迹线被配置为与第一组多对导电通孔电连接，并将虚拟导电迹线和一对虚拟导电通孔保持在未使用和电浮动状态。

公开(公告)号：US20050254309A1

公开(公告)日：2005-11-17

申请号：US10976628

申请日：2004-10-29

申请人： Oh-Suk Kwon ,  June Lee

发明人： Oh-Suk Kwon ,  June Lee

IPC分类号： G11C16/12 ,  G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： A program method of a non-volatile memory device comprises setting a string select line to a predetermined voltage, setting a selected word line to a program voltage and unselected word lines to a pass voltage respectively. The program voltage is varied according to an arrangement of the selected word line. Problems arising from capacitive coupling between adjacent signal lines are alleviated.

摘要翻译： 非易失性存储器件的编程方法包括将串选择线设置为预定电压，将所选择的字线设置为编程电压，将未选字线设置为通过电压。 编程电压根据所选字线的布置而变化。 相邻信号线之间电容耦合产生的问题得到缓解。

公开(公告)号：US06529420B2

公开(公告)日：2003-03-04

申请号：US10046956

申请日：2002-01-14

申请人： June Lee ,  Young-Ho Lim

发明人： June Lee ,  Young-Ho Lim

IPC分类号： G11C700

CPC分类号： G11C29/789 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/28

摘要： A redundant decoder circuit stores a repair address in electrically erasable and programmable memory, thereby allowing a redundant memory cell array to be tested before a repair operation is performed. The decoder circuit can include an address storage circuit having a plurality of electrically erasable and programmable memory cells arranged to store address data corresponding to a defective cell. A comparison circuit coupled to the address storage circuit generates an information signal responsive to the address data and an externally applied address. A redundant enable control unit can be adapted and arranged to enable and disable the redundant decoder circuit responsive to the state of an electrically erasable and programmable memory cell that indicates whether a main memory cell array has any defective cells.

公开(公告)号：USD367878S

公开(公告)日：1996-03-12

申请号：US028307

申请日：1994-09-12

申请人： June Lee ,  Jeffrey Smith ,  Gray Holland

设计人： June Lee ,  Jeffrey Smith ,  Gray Holland

公开(公告)号：US08699272B2

公开(公告)日：2014-04-15

申请号：US13473164

申请日：2012-05-16

申请人： June Lee ,  Fred Jaffin, III

发明人： June Lee ,  Fred Jaffin, III

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G06F11/1068 ,  G06F2212/202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26 ,  G11C16/349

摘要： For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the programming operation, and adjusting a program starting voltage level of one or more program pulses applied to the one or more memory cells during a subsequent programming operation in response, at least in part, to the number of program pulses required to program the sample of the one or more memory cells programmed during the prior programming operation.

摘要翻译： 对于一个实施例，编程方法包括在编程操作期间对存储器件的一个或多个存储器单元进行编程，在存储器件内部确定编程所述存储器器件的一个或多个存储单元的样本所需的编程脉冲数 在编程操作期间调整存储器件，以及在随后的编程操作期间调整施加到所述一个或多个存储器单元的一个或多个编程脉冲的程序启动电压电平，至少部分地响应于编程所需的编程脉冲的数量 在先前编程操作期间编程的一个或多个存储器单元的样本。

公开(公告)号：US20120311297A1

公开(公告)日：2012-12-06

申请号：US13152543

申请日：2011-06-03

申请人： June Lee ,  Terry M. Grunzke ,  Dean Nobunaga

发明人： June Lee ,  Terry M. Grunzke ,  Dean Nobunaga

IPC分类号： G06F12/10

CPC分类号： G06F13/4247 ,  G11C29/883

摘要： Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.

摘要翻译： 描述的实施例包括存储器设备内的逻辑单元，其中控制电路被配置为将逻辑单元地址分配给逻辑单元。 还公开了包括以菊花链配置布置的多个逻辑单元和将逻辑单元地址分配给逻辑单元的方法的装置。

公开(公告)号：US20110164453A1

公开(公告)日：2011-07-07

申请号：US13051221

申请日：2011-03-18

申请人： June Lee

发明人： June Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C2216/14

摘要： A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.

摘要翻译： 一种用于在多平面闪存中执行存储器操作的系统和方法。 命令和地址被顺序地提供给存储器以用于存储器平面中的存储器操作。 顺序地启动存储器操作，并且在另一存储器平面的存储器操作期间启动至少一个存储器平面的存储器操作。 在一个实施例中，多个编程电路中的每一个与相应的存储器平面相关联，并且可操作以响应于编程信号将数据编程到相应的存储器平面，并且当其被启用时。 耦合到多个编程电路的控制逻辑响应于存储器接收程序命令而产生编程信号，并进一步产生编程使能信号，以单独使编程电路中的每一个能够对编程信号做出响应，并将数据错开编程到每个存储器 飞机

公开(公告)号：US07821848B2

公开(公告)日：2010-10-26

申请号：US12606618

申请日：2009-10-27

申请人： June Lee

发明人： June Lee

IPC分类号： G11C11/00

CPC分类号： G11C16/10

摘要： A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second command latch input, and a command latch output, the first command latch input to couple to the command decoder output, and the second command latch input to couple to a write command output of an internal clock control generator; and a command register including a first command register input and a second command register input, the first command register input to couple to the command latch output, and the second command register input to couple to an internal latch command output of the internal clock control generator. Additional apparatus, systems, and methods are disclosed.

摘要翻译： 一种闪速存储器，包括具有至少一个外部输入以接收至少一个命令的第一锁存器，至少一个存储器地址和多个数据位，耦合到第一锁存器输出的命令解码器; 包括第一命令锁存器输入，第二命令锁存器输入和命令锁存器输出的命令锁存器，用于耦合到命令解码器输出的第一命令锁存器输入，以及耦合到第二命令锁存器输入的写命令输出 内部时钟控制发生器; 以及包括第一命令寄存器输入和第二命令寄存器输入的命令寄存器，输入到命令锁存器输出的第一命令寄存器以及耦合到内部时钟控制生成器的内部锁存命令输出的第二命令寄存器输入 。 公开了附加装置，系统和方法。

公开(公告)号：US07738294B2

公开(公告)日：2010-06-15

申请号：US12368666

申请日：2009-02-10

申请人： June Lee

发明人： June Lee

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621

摘要： Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first portion of a programming operation if a second or a fourth data state is desired, while memory cells remain in the first Vt distribution if the first or a third data state is desired. During a second portion of the programming operating, if the third data state is desired, those memory cells are shifted from the first Vt distribution to a third Vt distribution higher than the second Vt distribution and, if the fourth data state is desired, those memory cells are shifted from the second Vt distribution to a fourth Vt distribution higher than the third Vt distribution.

摘要翻译： 公开了诸如用于编程多电平单元NAND存储器阵列以便于减少程序干扰的方法和装置。 在一种这样的方法中，如果需要第二或第四数据状态，则在编程操作的第一部分期间，存储器单元从第一Vt分布移位到高于第一Vt分布的第二Vt分布，而存储单元保留在 如果需要第一或第三数据状态，则首先进行Vt分配。 在编程操作的第二部分期间，如果需要第三数据状态，那些存储单元从第一Vt分布移位到高于第二Vt分布的第三Vt分布，并且如果需要第四数据状态，那些存储器 单元从第二Vt分布移位到高于第三Vt分布的第四Vt分布。

公开(公告)号：US07679961B2

公开(公告)日：2010-03-16

申请号：US11739732

申请日：2007-04-25

申请人： June Lee ,  Fred Jaffin

发明人： June Lee ,  Fred Jaffin

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G06F11/1068 ,  G06F2212/202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26 ,  G11C16/349

摘要： For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.

摘要翻译： 对于一个实施例，施加到一个或多个存储器单元的一个或多个编程脉冲的程序启动电压至少部分地响应于先前需要编程的一个或多个存储器单元和/或 施加到一个或多个存储器单元的一个或多个擦除脉冲的擦除开始电压基于先前需要擦除一个或多个存储单元的擦除脉冲数。 对于另一个实施例，施加到一个或多个存储器单元的一个或多个编程和/或擦除脉冲的程序启动电压电平和/或擦除开始电压电平至少部分地响应于多个编程/擦除 先前施加到一个或多个存储器单元的循环。