公开(公告)号：US20100072961A1

公开(公告)日：2010-03-25

申请号：US12236003

申请日：2008-09-23

申请人： Stephen V. Kosonocky ,  Samuel D. Naffziger ,  Visvesh S. Sathe

发明人： Stephen V. Kosonocky ,  Samuel D. Naffziger ,  Visvesh S. Sathe

IPC分类号： G05F1/56 ,  G05F1/62

CPC分类号： H01L25/16 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0262 ,  H05K2201/10378 ,  Y10T307/406 ,  H01L2224/0401

摘要： A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.

摘要翻译： 公开了一种包括被称为集成电路插入器的电子设备的装置。 集成电路包括电压调节器模块。 插入器附接到诸如另一集成电路的电子设备，并且便于对电子设备的电力的控制和分配。 集成电路插入器还可以在附接的电子设备和另一电子设备之间进行信令。 集成电路插入器上的电压调节器模块可以被配置为向附接的电子设备提供电压参考信号。 根据电子设备的工作要求，可以使能或禁止由集成电路插入器产生电压参考信号，并且可以调节电压参考信号的值。

公开(公告)号：US07289587B2

公开(公告)日：2007-10-30

申请号：US10830367

申请日：2004-04-22

申请人： Eric M. Rentschler ,  Samuel D. Naffziger

发明人： Eric M. Rentschler ,  Samuel D. Naffziger

IPC分类号： H04L7/04 ,  G06F13/14 ,  H03K19/0175

CPC分类号： G01R31/31704 ,  G01R31/31705 ,  G01R31/31717 ,  G01R31/31725

摘要： Systems, methods, and other embodiments associated with a repeatable communication system are disclosed. One example system for receiving signals from an electronic component over a plurality of point-to-point communication links comprises a repeatability logic operably connected to each of the plurality of point-to-point communication links and configured to apply a delay offset to the signals received to compensate for frequency changes in signal transmissions over the plurality of point-to-point communication links.

摘要翻译： 公开了与可重复通信系统相关联的系统，方法和其他实施例。 用于通过多个点对点通信链路从电子部件接收信号的一个示例系统包括可操作地连接到多个点对点通信链路中的每一个的重复性逻辑，并且被配置为对信号应用延迟偏移 被接收以补偿在多个点对点通信链路上的信号传输中的频率变化。

公开(公告)号：US07276952B2

公开(公告)日：2007-10-02

申请号：US11261337

申请日：2005-10-28

申请人： Jayen J. Desai ,  Samuel D. Naffziger

发明人： Jayen J. Desai ,  Samuel D. Naffziger

IPC分类号： G06F1/04 ,  H03B21/00

CPC分类号： G06F1/04 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0814

摘要： A method of generating a clock signal using a digital frequency synthesizer includes providing a base clock to the digital frequency synthesizer, comparing a phase of an output clock from the digital frequency synthesizer with a phase of a reference signal, and issuing at least one frequency control command to the digital frequency synthesizer to align the phases.

摘要翻译： 使用数字频率合成器生成时钟信号的方法包括：向数字频率合成器提供基本时钟，将来自数字频率合成器的输出时钟的相位与参考信号的相位进行比较，以及发出至少一个频率控制 命令到数字频率合成器对齐相位。

公开(公告)号：US07239494B2

公开(公告)日：2007-07-03

申请号：US10653760

申请日：2003-09-03

申请人： Samuel D. Naffziger

发明人： Samuel D. Naffziger

IPC分类号： H02H9/00

CPC分类号： H03K5/08 ,  H03K17/0822 ,  H03K2005/00065

摘要： A system and method can mitigate voltage fluctuations. According to one embodiment, a delay system provides a delayed version of a first reference signal as a function of a supply voltage. A comparator provides a control signal for controlling a protection device based on the delayed version of the first reference signal and a second reference signal. The amount of delay provided by the delay system defines a threshold based on which the comparator provides the control signal.

摘要翻译： 系统和方法可以减轻电压波动。 根据一个实施例，延迟系统提供作为电源电压的函数的第一参考信号的延迟版本。 比较器提供用于基于第一参考信号的延迟版本和第二参考信号来控制保护装置的控制信号。 由延迟系统提供的延迟量定义了基于比较器提供控制信号的阈值。

公开(公告)号：US06772277B2

公开(公告)日：2004-08-03

申请号：US09845387

申请日：2001-04-30

申请人： Samuel D. Naffziger

发明人： Samuel D. Naffziger

IPC分类号： G06F1300

CPC分类号： G11C11/412 ,  G11C8/16 ,  G11C11/419

摘要： A method of operating a static random access memory (SRAM) having a column clear function by performing write operations using a two step process. To perform a write, each cell in a row to be written is preset during a first step. Then, each cell that is to have a zero written to it is cleared using a column clear operation. A column of cells may be cleared by enabling all the rows for clearing, then asserting column clear control signals for each of the columns in the array to be cleared. A subset of columns of a plurality of rows may be cleared by asserting a plurality of column clear signals corresponding to the subset of columns and a plurality of work lines corresponding to the plurality of rows.

摘要翻译： 一种通过使用两步处理执行写操作来操作具有列清除功能的静态随机存取存储器（SRAM）的方法。 要执行写入，在第一步中预设要写入的行中的每个单元格。 然后，使用列清除操作清除要写入零的每个单元。 可以通过启用所有行清除单元格列，然后为要清除的数组中的每个列确定列清除控制信号。 通过断言对应于列的子集的多个列清除信号和对应于多个行的多个工作线，可以清除多行的列的子集。

公开(公告)号：US06675118B2

公开(公告)日：2004-01-06

申请号：US09812660

申请日：2001-03-19

申请人： John D Wanek ,  Samuel D. Naffziger

发明人： John D Wanek ,  Samuel D. Naffziger

IPC分类号： G06F1900

CPC分类号： G01R31/318357 ,  G01R31/3173 ,  G01R31/318307 ,  G06F17/5036

摘要： The present invention includes a system for and a method of determining noise characteristics of a circuit of an integrated circuit. The circuit is classified based on its topology and measured circuit parameters. Noise characteristics are retrieved using the circuit classification and circuit parameters to calculate a noise response. Classification and characterization may be performed on each individual input.

摘要翻译： 本发明包括一种用于确定集成电路的电路的噪声特性的系统和方法。 该电路根据其拓扑和测量电路参数进行分类。 使用电路分类和电路参数检索噪声特性，以计算噪声响应。 可以对每个单独的输入执行分类和表征。

公开(公告)号：US06606720B1

公开(公告)日：2003-08-12

申请号：US09510006

申请日：2000-02-22

申请人： Samuel D. Naffziger

发明人： Samuel D. Naffziger

IPC分类号： G01R3128

CPC分类号： G01R31/318541 ,  G11C19/00 ,  G11C19/28 ,  H03K3/0375

摘要： Scan chain links which step data through a scan chain using only a single control signal, and which require a reduced number of transistors to scan data into and out of a latch. One scan chain link, which allows the output of a scanned latch to “wiggle”, uses eight transistors and only a single control signal. Another scan chain link, which prevents the output of a scanned latch from “wiggling”, and which allows data to be maintained in a latch during a scan operation if it is so desired, uses twenty-five transistors and two control signals: one control signal for stepping data through a scan chain, and an additional control signal for preventing the output of a scanned latch from wiggling.

摘要翻译： 扫描链路，其通过扫描链仅使用单个控制信号进行数据传输，并且需要减少数量的晶体管来扫描数据进出锁存器。 允许扫描的锁存器的输出“摆动”的一个扫描链路链路使用八个晶体管和仅一个控制信号。 另一个扫描链链路，如果需要，可以防止扫描的锁存器的输出“摆动”，并且允许在扫描操作期间将数据保持在锁存器中，使用二十五个晶体管和两个控制信号：一个控制 用于通过扫描链进行步进数据的信号，以及用于防止扫描的闩锁的输出摆动的附加控制信号。

公开(公告)号：US06301186B1

公开(公告)日：2001-10-09

申请号：US09845383

申请日：2001-04-30

申请人： Samuel D. Naffziger

发明人： Samuel D. Naffziger

IPC分类号： G11C816

CPC分类号： G11C8/16

摘要： An SRAM that has a column clear function with only three vertical lines and six total lines across a cell and a method of operating that cell and an array of those cells. Instead of two bit lines per port and two access devices per port as in a traditional SRAM cell, one bit line and one access device per port is used. In addition, one additional bit line, one additional word line, and two devices in series are used to perform the column clear operation and complete a write operation. The cell is operated by performing write operations using a two step process. To perform a write, each cell in a row to be written is preset during a first step. Then, each cell that is to have a zero written to it is cleared using the additional bit line and additional word line to address the cells to be cleared. A column of cells may be cleared by enabling all the rows for clearing, then asserting column clear control signals for each of the columns in the array to be cleared.

摘要翻译： 具有列清晰功能的SRAM，其中仅有三条垂直线和六条总线，以及一个操作该单元格和一组阵列的单元格的方法。 在传统的SRAM单元中，代替每个端口两个位线和每个端口两个访问设备，每个端口使用一个位线和一个访问设备。 另外，使用一个附加位线，一个附加字线和两个串联的器件来执行列清零操作并完成写操作。 通过使用两步过程执行写入操作来操作单元。 要执行写入，在第一步中预设要写入的行中的每个单元格。 然后，使用附加位线和附加字线清除写入零的每个单元，以寻址要清除的单元。 可以通过启用所有行清除单元格列，然后为要清除的数组中的每个列确定列清除控制信号。

公开(公告)号：US5892698A

公开(公告)日：1999-04-06

申请号：US628178

申请日：1996-04-04

申请人： Samuel D. Naffziger

发明人： Samuel D. Naffziger

IPC分类号： G06F7/544 ,  G06F7/38

CPC分类号： G06F7/5443 ,  G06F2207/3832 ,  G06F7/483 ,  G06F7/49957

摘要： A fully 2's complement FMAC (floating-point multiply accumulate unit) produces an unrounded output. The unrounded output is associated with a single INC bit, and is provided for early delivery as an FMAC operand. The INC bit is set using rounding logic which anticipates how a 2's complement conversion will affect a number, and then sets the INC bit in response to a rounding mode, and current L, G, S and sign bits. The rounding logic is configured to implement a truth table which demonstrates that rounding and 2's complement incrementation are mutually exclusive. When a bypassed result is received as an input to an FMAC, a delayed incrementer merges the unrounded C operand with its INC bit. The C incrementer and additional 2's complement conversion logic are placed approximately parallel with the multiply unit so that no additional delay is incurred in the FMAC's critical path. An INC bit corresponding to an A or B operand is absorbed within the FMAC's multiply unit. The FMAC allows an entire adder to be eliminated since the (A*B) result and C operand may be added in a single 2's complement adder rather than two carry propagate adders coupled to an end-around carry MUX.

摘要翻译： 完全2的补码FMAC（浮点乘法累加单元）产生未包围的输出。 未包围的输出与单个INC位相关联，并提供作为FMAC操作数的早期传送。 INC位使用舍入逻辑设置，预期2的补码转换将如何影响数字，然后根据舍入模式以及当前的L，G，S和符号位设置INC位。 舍入逻辑被配置为实现真值表，其证明舍入和2的补码递增是相互排斥的。 当接收到旁路结果作为FMAC的输入时，延迟加法器将未包围的C操作数与其INC位合并。 C增量器和附加2的补码转换逻辑与乘法单元大致平行放置，以便在FMAC的关键路径中不会产生额外的延迟。 对应于A或B操作数的INC位在FMAC的乘法单元内被吸收。 FMAC允许整个加法器被消除，因为（A * B）结果和C操作数可以被添加到单个2的补码加法器中，而不是耦合到末端进位MUX的两个进位传播加法器。

公开(公告)号：US5760608A

公开(公告)日：1998-06-02

申请号：US731817

申请日：1996-10-21

申请人： Samuel D. Naffziger ,  Ricky L. Pettit

发明人： Samuel D. Naffziger ,  Ricky L. Pettit

IPC分类号： G11C8/08 ,  H03K19/0185

CPC分类号： G11C8/08

摘要： A register dump providing enhanced efficiency by using a transmission gate for generating a register word line signal so as to reduce clock loading, and by using a complementary gate for generating a precharged pull-down signal so as to reduce discharge time and register word line capacitive loading.

摘要翻译： 通过使用传输门产生寄存器字线信号以减少时钟负载并通过使用互补栅极产生预充电下拉信号以减少放电时间和寄存器字线电容的寄存器转储提供增强的效率 加载。