公开(公告)号：US20130126820A1

公开(公告)日：2013-05-23

申请号：US13674519

申请日：2012-11-12

申请人： Chrong-Jung Lin ,  Ya-Chin King

发明人： Chrong-Jung Lin ,  Ya-Chin King

IPC分类号： H01L45/00

CPC分类号： H01L45/00 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： A variable and reversible resistive memory storage element and a memory storage module having the same are provided. The memory storage module comprises a select gate element and the resistive memory storage element. The select gate element comprises two source/drain regions. The resistive memory storage module comprises a first electrode, a first high-k dielectric layer and a second electrode. The first electrode is a semiconductor doping area, which is one of the two source/drain regions of the select gate element. The first high-k dielectric layer is formed on the first electrode to provide a variable resistance. The second electrode is a first metal gate formed on the first high-k dielectric layer.

摘要翻译： 提供了可变和可逆的电阻性存储器存储元件和具有该可变存储器存储元件的存储器存储模块 存储器存储模块包括选择栅极元件和电阻存储器存储元件。 选择栅极元件包括两个源极/漏极区域。 电阻式存储器存储模块包括第一电极，第一高k电介质层和第二电极。 第一电极是半导体掺杂区域，其是选择栅极元件的两个源极/漏极区域之一。 第一高k电介质层形成在第一电极上以提供可变电阻。 第二电极是形成在第一高k电介质层上的第一金属栅极。

公开(公告)号：US08093649B2

公开(公告)日：2012-01-10

申请号：US12408933

申请日：2009-03-23

申请人： Chrong-Jung Lin ,  Ya-Chin King

发明人： Chrong-Jung Lin ,  Ya-Chin King

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825

摘要： A flash memory cell includes a substrate, a source, a drain, a first oxide, a second oxide, a floating gate and a control gate. The source and a drain are formed in the substrate separately, and are doped with N-type ions. The first oxide is formed on the substrate. The floating gate is formed on the first oxide, wherein the floating gate is doped with P-type ions. The second oxide formed on the floating gate. The control gate formed on the second oxide.

摘要翻译： 闪存单元包括衬底，源极，漏极，第一氧化物，第二氧化物，浮动栅极和控制栅极。 源极和漏极分别形成在衬底中，并掺杂有N型离子。 在基板上形成第一氧化物。 浮置栅极形成在第一氧化物上，其中浮栅掺杂有P型离子。 在浮栅上形成的第二氧化物。 形成在第二氧化物上的控制栅极。

公开(公告)号：US20110260292A1

公开(公告)日：2011-10-27

申请号：US12859025

申请日：2010-08-18

申请人： Chrong-Jung Lin ,  Ya Chin King ,  Yi-Hung Tsai

发明人： Chrong-Jung Lin ,  Ya Chin King ,  Yi-Hung Tsai

IPC分类号： H01L29/73

CPC分类号： H01L29/735 ,  H01L29/405 ,  H01L29/456

摘要： A bipolar junction transistor having a carrier trapping layer, comprises a semi-conductor substrate including a well with a first type ions formed thereon; two impurity regions with a second type ions formed opposite with each other over the well; an insulation layer over the well, and edges extend over the second two impurity regions; and a carrier trapping layer formed over the insulation layer.

摘要翻译： 具有载流子俘获层的双极结型晶体管包括半导体基板，其包括在其上形成有第一类型离子的阱; 具有在阱上彼此相对形成的具有第二类型离子的两个杂质区; 阱上方的绝缘层，并且边缘在第二两个杂质区域上延伸; 以及形成在所述绝缘层上的载流子捕获层。

公开(公告)号：US20090278781A1

公开(公告)日：2009-11-12

申请号：US12344268

申请日：2008-12-25

申请人： Chrong-Jung Lin ,  Ya-Chin King

发明人： Chrong-Jung Lin ,  Ya-Chin King

IPC分类号： G09G3/36

CPC分类号： G09G3/3233 ,  G09G2300/0847 ,  G09G2320/0295 ,  G09G2320/043

摘要： A tunable current driver comprising a semiconductor memory device and a selective transistor is provided, in which one of the source/drain pair of the semiconductor memory device is electrically coupled with a lighting device, and one of the source/drain pair of the selective transistor is electrically coupled with the gate electrode of the semiconductor memory device. The semiconductor memory device not only acts as “drive transistor” to drive the lighting device, but also is capable of adjusting the threshold voltage thereof.

摘要翻译： 提供了一种包括半导体存储器件和选择性晶体管的可调电流驱动器，其中半导体存储器件的源极/漏极对中的一个与照明器件电耦合，并且选择晶体管的源极/漏极对之一 与半导体存储器件的栅电极电耦合。 半导体存储器件不仅用作“驱动晶体管”来驱动照明器件，而且还能够调节其阈值电压。

公开(公告)号：US20080057645A1

公开(公告)日：2008-03-06

申请号：US11831443

申请日：2007-07-31

申请人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Ya-Chin King

发明人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Ya-Chin King

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/7833

摘要： The fabricating method of a thick gate dielectric layer transistor is disclosed. A substrate including a first and a second regions and isolation structures is provided. A pad layer and a masking layer are formed on the substrate between the isolation structures. After the masking layer and the pad layer in the second region are removed, a dielectric layer and a conductive layer are sequentially formed on the substrate. The conductive layer, the dielectric layer and the pad layer are patterned to form a first gate structure in the first region and a second gate structure in the second region. A first source region and a first drain region are respectively formed in the substrate adjacent to the first gate structure, and a second source region and a second drain region are formed respectively in the substrate adjacent to the second gate structure.

摘要翻译： 公开了一种厚栅介质层晶体管的制造方法。 提供了包括第一和第二区域和隔离结构的衬底。 在隔离结构之间的衬底上形成衬垫层和掩模层。 在除去第二区域中的掩模层和焊盘层之后，在衬底上依次形成介电层和导电层。 将导电层，电介质层和焊盘层图案化以在第一区域中形成第一栅极结构，在第二区域中形成第二栅极结构。 第一源极区域和第一漏极区域分别形成在与第一栅极结构相邻的衬底中，并且第二源极区域和第二漏极区域分别形成在与第二栅极结构相邻的衬底中。

公开(公告)号：US20080017917A1

公开(公告)日：2008-01-24

申请号：US11778226

申请日：2007-07-16

申请人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Ya-Chin King

发明人： Chrong-Jung Lin ,  Hsin-Ming Chen ,  Ya-Chin King

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L29/7881 ,  H01L21/76829 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/66825

摘要： A non-volatile memory having an isolation structure, a floating gate transistor, a specific dielectric layer and an erase gate is provided. The isolation structure is disposed in a substrate to define an active region. The floating gate transistor having a floating gate, a tunneling dielectric layer, a first source/drain region and a second source/drain region is disposed on the substrate. The floating gate is disposed on the substrate and runs across the active region. The tunneling dielectric layer is disposed between the floating gate and the substrate. The first source/drain region and the second source/drain region are disposed in the substrate at the sides of the floating gate, respectively. The specific dielectric layer serves as an inter-layer dielectric layer, which is disposed on top of the floating gate. The erase gate is a conductive plug disposed upon the specific dielectric layer.

摘要翻译： 提供具有隔离结构的非易失性存储器，浮置栅极晶体管，特定介质层和擦除栅极。 隔离结构设置在衬底中以限定有源区。 具有浮置栅极，隧道电介质层，第一源极/漏极区域和第二源极/漏极区域的浮置栅极晶体管设置在衬底上。 浮置栅极设置在衬底上并跨越有源区域。 隧道介电层设置在浮置栅极和衬底之间。 第一源极/漏极区域和第二源极/漏极区域分别设置在浮置栅极的侧面的衬底中。 比电介质层用作层间电介质层，其设置在浮动栅极的顶部。 擦除栅极是设置在特定电介质层上的导电插塞。

公开(公告)号：US20070278556A1

公开(公告)日：2007-12-06

申请号：US11442119

申请日：2006-05-30

申请人： Ya-Chin King ,  Chrong-Jung Lin

发明人： Ya-Chin King ,  Chrong-Jung Lin

IPC分类号： H01L29/788

CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L29/40117 ,  H01L29/66833

摘要： A twin non-volatile memory cell on unit device and method of operating the same are disclosed. The device is formed in the n-well and compatible with CMOS processes comprising a selecting gate, two ONO spacers, a p+ source/drain, and n extended source/drain. To program the cells, two strategies can be taken. One is by a band to band hot electron injection can be carried out. The other is by channel hot hole induced hot electron injection. To read the right cell of the twin nonvolatile cells, a reverse read is taken so as to shield the left cell. In the reading process, the biased on the selecting gate and the source electrode have to make sure the tapered main channel beneath selecting gate has its narrower end through the depletion boundary to connect the second channel beneath the extended source. To erase the datum in the selected cell, two approaching can be carried out. One is by FN erase, the other is by band to band induced hot hole injection.

摘要翻译： 公开了一种单元设备上的双非易失性存储单元及其操作方法。 该器件形成在n阱中，并且与包括选择栅极，两个ONO间隔物，p +源极/漏极和n个扩展源极/漏极的CMOS工艺兼容。 为了对细胞进行编程，可以采用两种策略。 一种是通过带式热电子注入可以进行。 另一种是通道热孔诱导热电子注入。 为了读取双非易失性单元的正确单元格，进行反向读取以屏蔽左单元格。 在读取过程中，偏置在选择栅极和源电极上必须确保选择栅极下方的锥形主通道具有通过耗尽边界的较窄端，以将扩展源下方的第二通道连接。 要删除所选单元格中的原点，可以进行两次逼近。 一种是通过FN擦除，另一种是通过频带带诱导热空穴注入。

公开(公告)号：US20070272995A1

公开(公告)日：2007-11-29

申请号：US11802369

申请日：2007-05-22

申请人： Ya-Chin King ,  Chrong-Jung Lin

发明人： Ya-Chin King ,  Chrong-Jung Lin

IPC分类号： H01L31/00

CPC分类号： H01L31/0384 ,  H01L27/14609 ,  H01L31/04 ,  Y02E10/50

摘要： A photosensitive device is provided. The photosensitive device can be an image sensor or a solar cell. The photosensitive device includes a driving circuit such as photo sensor circuit or solar cell circuit, and a nano-crystal layer. The nano-crystal layer is located above the driving circuit and includes a silicon compound layer and plural nano-crystal particles. The nano-crystal particles are distributed in the silicon compound layer and capable of capturing photon and further converting into photocurrent.

摘要翻译： 提供感光装置。 感光装置可以是图像传感器或太阳能电池。 感光装置包括诸如光传感器电路或太阳能电池电路的驱动电路和纳米晶体层。 纳米晶体层位于驱动电路的上方，包括硅化合物层和多个纳米晶体颗粒。 纳米晶粒分布在硅化合物层中，能够捕获光子并进一步转化为光电流。

公开(公告)号：US20070264766A1

公开(公告)日：2007-11-15

申请号：US11746061

申请日：2007-05-09

申请人： Chrong-Jung Lin ,  Ya-Chin King

发明人： Chrong-Jung Lin ,  Ya-Chin King

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117

摘要： A nitride/oxide/semiconductor (NOS) non-volatile memory cell formed in an n-well, having no control gate and capable of storing two bits is provided. The NOS non-volatile memory cell includes at least one NO (nitride layer, oxide layer) storage gate capable of storing one bit of data in the nitride layer adjacent to the source and the drain, respectively. The source and the drain are regions heavily doped with p-type impurities. The NOS non-volatile memory cell is capable of doubling the storage capacity of a flash memory chip having the same size.

摘要翻译： 提供了形成在n阱中的不具有控制栅极并且能够存储两个位的氮化物/氧化物/半导体（NOS）非易失性存储单元。 NOS非易失性存储单元包括至少一个能够分别在与源极和漏极相邻的氮化物层中存储一位数据的NO（氮化物层，氧化物层）存储栅极。 源极和漏极是重掺杂有p型杂质的区域。 NOS非易失性存储单元能够将具有相同尺寸的闪存芯片的存储容量加倍。

公开(公告)号：US20050017287A1

公开(公告)日：2005-01-27

申请号：US10623912

申请日：2003-07-21

申请人： Yue-Der Chih ,  Chrong-Jung Lin ,  Sheng-Wei Tsao ,  Chin-Huang Wang

发明人： Yue-Der Chih ,  Chrong-Jung Lin ,  Sheng-Wei Tsao ,  Chin-Huang Wang

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L33/00

CPC分类号： G11C16/0433 ,  H01L27/115

摘要： This invention provides a memory array and it support signals and a method for byte access for programming, erasing and reading memory cells. The advantage of this array and method is the ability to access bytes for program, erase, and read operations. This array and method uses an added isolation transistor to isolate the high voltage from the unselected byte. In addition, it utilizes a separate source line for each byte in a row. This source line is also shared by a byte in a different row. The array has very little peripheral circuit overhead requirement and it avoids programming disturbances of unselected memory cells.

摘要翻译： 本发明提供了一种存储器阵列，并且它支持信号和用于编程，擦除和读取存储器单元的字节访问的方法。 该数组和方法的优点是可以访问字节进行程序，擦除和读取操作。 该阵列和方法使用添加的隔离晶体管将高电压与未选择的字节隔离开来。 此外，它为一行中的每个字节使用单独的源行。 该源行也由不同行中的一个字节共享。 阵列具有非常少的外围电路开销要求，并且避免了未选择的存储单元的编程干扰。