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公开(公告)号：US07805550B2
公开(公告)日：2010-09-28
申请号：US11032226
申请日：2005-01-11
CPC分类号： G06F13/24 , G06F1/3228
摘要： A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode. This provides a particularly efficient technique for managing a polling loop within the data processing apparatus.
摘要翻译： 提供了一种用于管理轮询循环的数据处理装置和方法。 数据处理装置包括主处理单元和辅助处理单元，可操作以代表主处理单元执行任务。 辅助处理单元可操作以在任务完成时设置完成字段，并且主处理单元可操作地轮询完成字段以便确定任务是否已经完成。 如果在轮询完成字段时，主处理单元确定任务尚未完成的阈值次数，则主处理单元可操作以进入省电模式。 当完成任务时，辅助处理单元可操作地在连接主处理单元和辅助处理单元的路径上发出通知。 主处理单元在接收到退出省电模式的通知时被布置。 这提供了一种用于管理数据处理装置内的轮询循环的特别有效的技术。
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公开(公告)号：US20100235579A1
公开(公告)日：2010-09-16
申请号：US12223173
申请日：2006-09-18
CPC分类号： G06F12/127 , G06F12/0862
摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.
摘要翻译： 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓冲存储器，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关联的处理单元执行访问时的数据值 指令序列 提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。 然后，对于每个高速缓存，缓存维护逻辑被设置为实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别的任何优选的执行，从该高速缓存中选择一个或多个数据值 在那个缓存中。 已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。
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公开(公告)号：US07797520B2
公开(公告)日：2010-09-14
申请号：US11170083
申请日：2005-06-30
IPC分类号： G06F9/00
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A data processing apparatus including a prefetch unit for prefetching the instructions from a memory, branch prediction logic and a branch target cache for storing predetermined information about branch operations executed by the processor. The information includes identification of an instruction specifying a branch operation, a target address for said branch operation and a prediction as to whether said branch operation is taken or not. The prefetch unit accesses said branch target cache at least one clock cycle prior to fetching an instruction from said memory, to determine if there is predetermined information corresponding to said instruction stored within said branch target cache.
摘要翻译： 一种数据处理装置，包括用于从存储器预取指令的预取单元，分支预测逻辑和用于存储关于由处理器执行的分支操作的预定信息的分支目标高速缓存。 该信息包括指定分支操作的指令的标识，用于所述分支操作的目标地址以及是否采用所述分支操作的预测。 预取单元在从所述存储器取出指令之前至少一个时钟周期访问所述分支目标高速缓存，以确定是否存在与存储在所述分支目标高速缓存中的所述指令相对应的预定信息。
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公开(公告)号：US07757027B2
公开(公告)日：2010-07-13
申请号：US12213470
申请日：2008-06-19
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Richard Roy Grisenthwaite , Stuart David Biles
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Richard Roy Grisenthwaite , Stuart David Biles
IPC分类号： G06F13/00
CPC分类号： G06F13/4221
摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.
摘要翻译： 集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写 ）。 当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。
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35.发明申请Data processing apparatus and method for controlling access to secure memory by virtual machines executing on processing circuirty 有权用于通过处理循环执行的虚拟机来控制对安全存储器的访问的数据处理装置和方法公开(公告)号：US20090222816A1
公开(公告)日：2009-09-03
申请号：US12379082
申请日：2009-02-12
IPC分类号： G06F9/455
CPC分类号： G06F12/145
摘要： A data processing apparatus and method are provided for controlling access to secure memory by virtual machines executing on processing circuitry. The processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system is provided for storing data for access by the processing circuitry, the memory system comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the secure memory only being accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. A trusted virtual machine identifier is maintained and managed by the hypervisor software, with the hypervisor software setting the trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. Accordingly, in response to the access request issued by the current virtual machine, the address translation circuitry is only able to cause the modified access request to be issued as a secure access request specifying a physical address within the secure memory if the trusted virtual machine identifier is set. By such an approach, the hypervisor software is able to support multiple virtual machines at least some of which have access to secure memory under conditions controlled by the hypervisor software.
摘要翻译： 提供了一种数据处理装置和方法，用于通过在处理电路上执行的虚拟机来控制对安全存储器的访问。 处理电路执行管理程序软件以支持处理电路上的多个虚拟机的执行。 提供了一种用于存储由处理电路进行访问的数据的存储器系统，该存储器系统包括用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器，该安全存储器仅可通过安全访问请求访问。 地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定 物理地址。 由管理程序软件维护和管理可信赖的虚拟机标识符，如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信虚拟机标识符。 因此，响应于当前虚拟机发出的访问请求，地址转换电路仅能够将修改的访问请求作为指定安全存储器内的物理地址的安全访问请求发出，如果可信虚拟机标识符 被设置。 通过这种方法，管理程序软件能够支持多个虚拟机，其中至少一些虚拟机在由管理程序软件控制的条件下可以访问安全存储器。
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公开(公告)号：US20090125756A1
公开(公告)日：2009-05-14
申请号：US11984221
申请日：2007-11-14
IPC分类号： G06F11/34
CPC分类号： G06F11/3476 , G06F11/348 , G06F2201/865
摘要： A data processing apparatus is provided, comprising monitored circuitry for performing activities, trace circuitry for producing a stream of trace elements representative of at least some of these activities, and detection circuitry for detecting the occurrence of a predetermined subset of the activities for which the trace circuitry is producing trace elements. When an activity in that predetermined subset of activities is detected a timing indication is added to the stream of trace elements. Hence, the valuable trace bandwidth- may be preserved, by limiting the trace elements for which a timing indication is added into the trace stream to a predetermined subset of the activities for which trace elements are generated, and the valuable global or relative timing accuracy of those activities represented in the trace stream is retained, without flooding the trace stream with timing indications.
摘要翻译： 提供了一种数据处理装置，包括用于执行活动的被监测电路，用于产生表示这些活动中的至少一些的微量元素流的跟踪电路，以及检测电路，用于检测所述活动的预定子集的发生 电路正在产生微量元素。 当检测到该预定活动子集中的活动时，将定时指示添加到微量元素流。 因此，可以通过将跟踪流中添加定时指示的跟踪元素限制到生成微量元素的活动的预定子集，并将有价值的全局或相对定时精度保留在有价值的跟踪带宽中 在跟踪流中表示的那些活动被保留，而不会使跟踪流与时间指示淹没。
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公开(公告)号：US07426659B2
公开(公告)日：2008-09-16
申请号：US11085263
申请日：2005-03-22
IPC分类号： G06F11/00
CPC分类号： G06F11/079 , G06F11/2733
摘要： A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.
摘要翻译： 描述了具有中央处理单元4和诊断机构10的数据处理系统2.中央处理单元4可切换到能够恢复到正常操作模式的掉电模式。 当中央处理单元4恢复到正常操作模式时，诊断机构10禁止程序指令的执行，以允许对诊断机构进行适当的编程，使得立即上电代码和操作能被正确诊断。 通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。 程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。
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公开(公告)号：US06708317B2
公开(公告)日：2004-03-16
申请号：US10023835
申请日：2001-12-21
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G01R31/318544 , G01R31/31922 , G01R31/31937 , G06F17/5022
摘要： A microprocessor core 4 is modeled using an obscured model 22 of the core functionality and a non-obscured model 24 of the scan chains that in that particular instance are associated with the microprocessor core 4. Validation of the design of a scan chain controller 12 can be achieved using the non-obscured scan chain model 24. Different scan chain models 24 can be relatively easily provided to model different scan chain physical configurations whilst leaving the more difficult to produce obscured core model 22 unaltered.
摘要翻译： 使用核心功能的模糊模型22和扫描链的非遮蔽模型24来模拟微处理器核心4，在特定情况下，微处理器核心4与微处理器核心4相关联。扫描链控制器12的设计的验证 可以使用非遮蔽的扫描链模型24来实现。可以相对容易地提供不同的扫描链模型24以模拟不同的扫描链物理配置，同时使难以产生模糊的核心模型22变得更加困难。
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公开(公告)号：US09804851B2
公开(公告)日：2017-10-31
申请号：US13064257
申请日：2011-03-14
申请人： Richard Roy Grisenthwaite , David James Seal , Philippe Jean-Pierre Raphalen , Lee Douglas Smith
发明人： Richard Roy Grisenthwaite , David James Seal , Philippe Jean-Pierre Raphalen , Lee Douglas Smith
CPC分类号： G06F9/3016 , G06F9/3001 , G06F9/30112 , G06F9/3861 , G06F21/577 , G06F21/70 , G06F2221/2145
摘要： A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.
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公开(公告)号：US09753724B2
公开(公告)日：2017-09-05
申请号：US13200348
申请日：2011-09-23
CPC分类号： G06F9/30003 , G06F9/30072 , G06F9/30094 , G06F9/3842
摘要： A data processing apparatus, method and computer program that perform an operation on one data element such as a register and conditionally select either that register or a further register on which no operation has been performed. The apparatus includes an instruction decoder configured to decode at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. Data processing operations are controlled by the instruction decoder and the data processor is responsive to the decoded at least one conditional select instruction where the condition does not have the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.
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