公开(公告)号：US07242339B1

公开(公告)日：2007-07-10

申请号：US11333613

申请日：2006-01-17

申请人： Bao G. Truong ,  Joel D. Ziegelbein

发明人： Bao G. Truong ,  Joel D. Ziegelbein

IPC分类号： H03M1/78

CPC分类号： H03K17/6872 ,  H03K17/6874

摘要： A reference generator circuit has a resistor string between the potentials of the power supply voltage that is partitioned into a top string, a middle string, and a bottom string. PFET devices are used to couple the positive power supply voltage a selected node of the top string in response to first control signals and complementary second control signals are used to control NFET devices that couple the ground power supply voltage to a selected node of the bottom string. If a resistor is effectively removed from the top string a corresponding resistor is effectively added in the bottom string keeping the total resistance in the resistor string substantially constant. A pass gate network is used to select between nodes of the middle string as a vernier for generating small step sizes.

摘要翻译： 参考发生器电路在电源电压的电位之间具有分隔成顶部串，中间串和底部串的电阻串。 PFET装置用于响应于第一控制信号将正电源电压耦合到顶部串的所选节点，并且互补的第二控制信号用于控制将接地电源电压耦合到底部串的选定节点的NFET装置 。 如果从顶部串中有效地去除电阻器，则在底部串中有效地添加相应的电阻器，从而保持电阻串中的总电阻基本上恒定。 传递门网络用于在中间串的节点之间选择用于生成小步长的游标。

公开(公告)号：US20130141992A1

公开(公告)日：2013-06-06

申请号：US13312867

申请日：2011-12-06

申请人： Michael Ju Hyeok Lee ,  Bao G. Truong

发明人： Michael Ju Hyeok Lee ,  Bao G. Truong

IPC分类号： G11C7/00

CPC分类号： G11C14/0054 ,  G11C7/18 ,  G11C11/419

摘要： A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.

摘要翻译： 存储器包括形成行和列的存储器单元阵列。 阵列的行包括存储单元对。 存储器单元可以包括耦合到交叉耦合的反相器的交替侧的两个交叉耦合的反相器和两个通过装置。 存储器单元对的两个存储单元共享共同的对内位线。 相邻的存储单元对共享一个共同的对对位线。 为了对阵列的行和列中的存储单元对中的特定存储器单元执行数据读取操作，字线驱动电路传输字线激活信号以选择用于数据读取操作的行和该对中的特定一个 用于数据读取操作的存储单元。

公开(公告)号：US08239430B2

公开(公告)日：2012-08-07

申请号：US11869022

申请日：2007-10-09

申请人： David N. Ault ,  Emiliano Lozano ,  Bao G. Truong ,  Samuel I. Ward

发明人： David N. Ault ,  Emiliano Lozano ,  Bao G. Truong ,  Samuel I. Ward

IPC分类号： G06F7/00

CPC分类号： G06F7/5446

摘要： Performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. Execution of the CORDIC algorithm is begun. An error introduced by a truncated vector as a result of executing the CORDIC algorithm is pre-computed. The error is incorporated into a subsequent iteration of the CORDIC algorithm. Execution of the CORDIC algorithm is completed. The result of the CORDIC algorithm is stored.

摘要翻译： 使用坐标旋转数字计算机（CORDIC）算法进行计算。 开始执行CORDIC算法。 作为执行CORDIC算法的结果的截断向量引入的​​误差是预先计算的。 该错误被并入CORDIC算法的后续迭代中。 完成CORDIC算法的执行。 存储CORDIC算法的结果。

公开(公告)号：US20110141826A1

公开(公告)日：2011-06-16

申请号：US12635234

申请日：2009-12-10

申请人： Michael J. Lee ,  Bao G. Truong ,  Samuel I. Ward

发明人： Michael J. Lee ,  Bao G. Truong ,  Samuel I. Ward

IPC分类号： G11C7/10 ,  G11C8/08 ,  G11C7/00 ,  G06F17/50

CPC分类号： G06F12/0895 ,  G06F2212/1028 ,  G11C11/412 ,  Y02D10/13

摘要： A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

摘要翻译： 提供了一种机制，用于选通已被无效的高速缓存访​​问存储器中的任何行的读取访问。 高速缓存存取存储器中的地址解码器发送存储器访问到非门控字线驱动器和与存储器访问相关联的选通字线驱动器。 响应于非门控字线驱动器将存储器访问确定为读取访问，非门控字线驱动器将存储在有效位存储器单元中的数据输出到门控字线驱动器。 门控字线驱动器确定来自非门控字线驱动器的来自有效位存储器单元的数据是否响应于门控字线驱动器确定存储器访问作为读取访问而指示有效数据或无效数据，并且拒绝数据的输出 在与该门控字幕驱动器相关联的一行存储器单元响应于该数据无效。

公开(公告)号：US07788444B2

公开(公告)日：2010-08-31

申请号：US11609464

申请日：2006-12-12

申请人： Michael J. Lee ,  Bao G. Truong

发明人： Michael J. Lee ,  Bao G. Truong

IPC分类号： G06F13/00 ,  G06F13/28 ,  G11C15/00

CPC分类号： G11C15/04 ,  G06F12/1027

摘要： Mechanisms for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.

摘要翻译： 提供了诸如内容可寻址存储器（CAM）之类的关联存储器中多次命中（多重命中）检测的机制。 示例性实施例包括作为关联存储器的RAM侧条目进行放电的命中位线。 命中位线被预充电高，并被一系列在每个RAM侧行被访问时激活的设备拉低。 随着访问更多的RAM侧行，命中位线的电压降低。 命中位线驱动具有阈值设置的逆变器，使得等于或低于阈值的任何电压指示多重命中情况。 任何高于阈值的电压都表示单次击中或“无命中”情况。 因此，从命中位线的电压可以检测到存在多命中条件。

公开(公告)号：US07788443B2

公开(公告)日：2010-08-31

申请号：US11609416

申请日：2006-12-12

申请人： Michael J. Lee ,  Vinod Ramadurai ,  Bao G. Truong

发明人： Michael J. Lee ,  Vinod Ramadurai ,  Bao G. Truong

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F11/00 ,  G11C15/00

CPC分类号： G11C15/04 ,  G06F12/1027

摘要： A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.

摘要翻译： 提供了一种用于联想记忆中的透明多点校正的机制。 提供内容关联存储器（CAM）装置，其在检测到多重命中的情况下透明地且独立地执行精确的校正动作。 CAM阵列的字线被修改为包括有效位存储电路元件，其指示对应的字线是否有效。 在操作中，如果检测到多个命中，则将多次命中信号发送到主机系统，并且通过将其相关联的有效位存储电路元件设置为无效值或清除该值来使与多次命中相对应的CAM阵列中的特定条目无效 在相关联的有效位存储电路元件中。 作为多次命中的结果返回到主机系统的任何数据在主机系统中响应于多次命中的信令而无效。

公开(公告)号：US20080140925A1

公开(公告)日：2008-06-12

申请号：US11609464

申请日：2006-12-12

申请人： MICHAEL J. LEE ,  Bao G. Truong

发明人： MICHAEL J. LEE ,  Bao G. Truong

IPC分类号： G06F12/00

CPC分类号： G11C15/04 ,  G06F12/1027

摘要： An apparatus and method for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.

摘要翻译： 提供了诸如内容可寻址存储器（CAM）等关联存储器中的多命中（多次命中）检测的装置和方法。 示例性实施例包括作为关联存储器的RAM侧条目进行放电的命中位线。 命中位线被预充电高，并被一系列在每个RAM侧行被访问时激活的设备拉低。 随着访问更多的RAM侧行，命中位线的电压降低。 命中位线驱动具有阈值设置的逆变器，使得等于或低于阈值的任何电压指示多重命中情况。 任何高于阈值的电压都表示单次击中或“无命中”情况。 因此，从命中位线的电压可以检测到存在多命中条件。

公开(公告)号：US08375172B2

公开(公告)日：2013-02-12

申请号：US12761618

申请日：2010-04-16

申请人： Eddie K. Chan ,  Michael J. Lee ,  Ricardo H. Nigaglioni ,  Bao G. Truong

发明人： Eddie K. Chan ,  Michael J. Lee ,  Ricardo H. Nigaglioni ,  Bao G. Truong

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C11/00 ,  G11C7/00

CPC分类号： G11C7/22 ,  G06F12/0855 ,  G06F12/0895 ,  G11C11/412 ,  G11C11/413

摘要： A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.

摘要翻译： 提供了一种机制，用于在直写操作期间实现适当的写入。 响应于将存储器访问确定为直写操作，第一电路确定数据输入信号是处于第一状态还是第二状态。 响应于处于第二状态的数据输入信号，第一电路在第一状态下输出全局写入线信号。 响应于全局写入线信号处于第一状态，第二电路输出处于第二状态的列选择信号。 响应于列选择信号处于第二状态，第三电路将高速缓存存取存储器的下游读取路径保持在第一状态，使得由高速缓冲存储器阵列输出的数据处于第一状态。

公开(公告)号：US08006152B2

公开(公告)日：2011-08-23

申请号：US12351950

申请日：2009-01-12

申请人： Samuel I. Ward ,  Patrick R. Crosby ,  William D. Ramsour ,  Bao G. Truong

发明人： Samuel I. Ward ,  Patrick R. Crosby ,  William D. Ramsour ,  Bao G. Truong

IPC分类号： G01R31/28

CPC分类号： G01R31/318566 ,  G01R31/318547

摘要： A method comprises generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs). The plurality of faults detected by a first MISR and by a second MISR are identified. In the event the plurality of faults detected by the first MISR does not include any of the plurality of faults detected by the second MISR and the plurality of faults detected by the second MISR does not include any of the plurality of faults detected by the first MISR, the first MISR and the second MISR are coupled as an independent MISR pair. The test pattern is applied to the DUT to generate a scan chain output. The independent MISR pair captures the scan chain output to generate a test signature. The test signature is compared with a known good signature.

摘要翻译： 一种方法包括产生被测器件（DUT）的测试图案，其中DUT包括耦合到多个多输入移位寄存器（MISR）的多个扫描链。 识别由第一MISR和第二MISR检测到的多个故障。 在由第一MISR检测到的多个故障不包括由第二MISR检测到的多个故障中的任何一个故障的情况下，由第二MISR检测到的多个故障不包括由第一MISR检测到的多个故障中的任何一个 ，第一MISR和第二MISR作为独立MISR对耦合。 将测试模式应用于DUT以生成扫描链输出。 独立的MISR对捕获扫描链输出以生成测试签名。 将测试签名与已知的良好签名进行比较。

公开(公告)号：US20100180168A1

公开(公告)日：2010-07-15

申请号：US12351950

申请日：2009-01-12

申请人： Samuel I. Ward ,  Patrick R. Crosby ,  William D. Ramsour ,  Bao G. Truong

发明人： Samuel I. Ward ,  Patrick R. Crosby ,  William D. Ramsour ,  Bao G. Truong

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318566 ,  G01R31/318547

摘要： A method comprises generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs). The plurality of faults detected by a first MISR and by a second MISR are identified. In the event the plurality of faults detected by the first MISR does not include any of the plurality of faults detected by the second MISR and the plurality of faults detected by the second MISR does not include any of the plurality of faults detected by the first MISR, the first MISR and the second MISR are coupled as an independent MISR pair. The test pattern is applied to the DUT to generate a scan chain output. The independent MISR pair captures the scan chain output to generate a test signature. The test signature is compared with a known good signature.

摘要翻译： 一种方法包括产生被测器件（DUT）的测试图案，其中DUT包括耦合到多个多输入移位寄存器（MISR）的多个扫描链。 识别由第一MISR和第二MISR检测到的多个故障。 在由第一MISR检测到的多个故障不包括由第二MISR检测到的多个故障中的任何一个故障的情况下，由第二MISR检测到的多个故障不包括由第一MISR检测到的多个故障中的任何一个 ，第一MISR和第二MISR作为独立MISR对耦合。 将测试模式应用于DUT以生成扫描链输出。 独立的MISR对捕获扫描链输出以生成测试签名。 将测试签名与已知的良好签名进行比较。