公开(公告)号：US20130141997A1

公开(公告)日：2013-06-06

申请号：US13312945

申请日：2011-12-06

申请人： Michael Ju Hyeok Lee ,  Bao G. Truong

发明人： Michael Ju Hyeok Lee ,  Bao G. Truong

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C8/00

CPC分类号： G11C14/0054 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C11/419

摘要： A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory cell of the pair, the selected memory cell being an addressed memory cell while the remaining cell is an unaddressed memory cell. In response to a wordline enable signal, a pass gate in the addressed memory cell couples the addressed memory cell via a complement bitline to an evaluation gate that resolves the data from the read operation. During the read operation, the unaddressed memory cell couples via another pass gate to a true bitline that terminates without an evaluation gate to conserve energy.

摘要翻译： 存储器包括形成行和列的存储器单元阵列。 行包括存储单元对。 存储器单元可以包括耦合到交叉耦合的反相器的交替侧的两个交叉耦合的反相器和两个通过装置。 对于读取操作，字线驱动电路选择该对中的一个存储单元，所选择的存储单元是寻址存储单元，而剩余单元是未寻址存储单元。 响应于字线使能信号，寻址的存储器单元中的通过门经由补充位线将寻址的存储器单元耦合到评估门，其从读取操作中解析数据。 在读取操作期间，未寻址存储器单元经由另一个通道耦合到真正的位线，该位线在没有评估门的情况下终止以节省能量。

公开(公告)号：US20100027361A1

公开(公告)日：2010-02-04

申请号：US12185234

申请日：2008-08-04

申请人： Michael Ju Hyeok Lee ,  Bao G. Truong

发明人： Michael Ju Hyeok Lee ,  Bao G. Truong

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/413

摘要： An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.

摘要翻译： 信息处理系统（IHS）包括具有片上或片外SRAM阵列的处理器。 在读取操作之后，控制电路可以指示SRAM阵列进行预充电操作，或者替代地指示SRAM阵列进行均衡的位线电压操作。 读取操作可以遵循预充电操作或均衡位线电压操作。 如果位线对的均衡电压显示出更多的预定量的电压，则控制电路可以指示SRAM阵列进行均衡的位线电压操作。 否则，控制电路指示SRAM阵列在下一次读取操作之前进行预充电操作。

公开(公告)号：US20130141992A1

公开(公告)日：2013-06-06

申请号：US13312867

申请日：2011-12-06

申请人： Michael Ju Hyeok Lee ,  Bao G. Truong

发明人： Michael Ju Hyeok Lee ,  Bao G. Truong

IPC分类号： G11C7/00

CPC分类号： G11C14/0054 ,  G11C7/18 ,  G11C11/419

摘要： A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.

摘要翻译： 存储器包括形成行和列的存储器单元阵列。 阵列的行包括存储单元对。 存储器单元可以包括耦合到交叉耦合的反相器的交替侧的两个交叉耦合的反相器和两个通过装置。 存储器单元对的两个存储单元共享共同的对内位线。 相邻的存储单元对共享一个共同的对对位线。 为了对阵列的行和列中的存储单元对中的特定存储器单元执行数据读取操作，字线驱动电路传输字线激活信号以选择用于数据读取操作的行和该对中的特定一个 用于数据读取操作的存储单元。

公开(公告)号：US08014215B2

公开(公告)日：2011-09-06

申请号：US12635234

申请日：2009-12-10

申请人： Michael J. Lee ,  Bao G. Truong ,  Samuel I. Ward

发明人： Michael J. Lee ,  Bao G. Truong ,  Samuel I. Ward

IPC分类号： G11C7/00

CPC分类号： G06F12/0895 ,  G06F2212/1028 ,  G11C11/412 ,  Y02D10/13

摘要： A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

摘要翻译： 提供了一种机制，用于选通已被无效的高速缓存访​​问存储器中的任何行的读取访问。 高速缓存存取存储器中的地址解码器发送存储器访问到非门控字线驱动器和与存储器访问相关联的选通字线驱动器。 响应于非门控字线驱动器将存储器访问确定为读取访问，非门控字线驱动器将存储在有效位存储器单元中的数据输出到门控字线驱动器。 门控字线驱动器确定来自非门控字线驱动器的来自有效位存储器单元的数据是否响应于门控字线驱动器确定存储器访问作为读取访问而指示有效数据或无效数据，并且拒绝数据的输出 在与该门控字幕驱动器相关联的一行存储器单元响应于该数据无效。

公开(公告)号：US07673204B2

公开(公告)日：2010-03-02

申请号：US11773578

申请日：2007-07-05

申请人： Gahn W. Krishnakalin ,  Emiliano Lozano ,  Bao G. Truong ,  Samuel I. Ward

发明人： Gahn W. Krishnakalin ,  Emiliano Lozano ,  Bao G. Truong ,  Samuel I. Ward

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector wherein at least two of the coding schemes selected for encoding are different from one another, and wherein one of the available coding schemes represents non-encoded data. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to a plurality of decoders, wherein each decoder is adapted to recognize only one of the coding schemes represented by one of the bit patterns. The decoder recognizing the coding scheme of the data block decodes the bit pattern of the data block and generates the test vectors corresponding to the data block.

摘要翻译： 提供了一种使用非线性数据压缩的方法，以便产生用于在集成电路的扫描测试中使用的一组测试向量。 该方法包括以下步骤：首先设计该组测试向量，并为每个测试向量选择多个可用编码方案中的一个，其中选择用于编码的编码方案中的至少两个彼此不同，并且其中一个可用编码 方案表示非编码数据。 该方法还包括操作随机模式发生器以产生数据块，每个对应于一个测试向量，其中与给定测试向量相对应的数据块用表示给定测试向量的编码方案的比特模式进行编码。 相应的数据块还具有小于给定测试向量的位长度的位长度。 每个数据块被路由到多个解码器，其中每个解码器适于仅识别由一个位模式表示的编码方案之一。 识别数据块的编码方式的解码器对数据块的位模式进行解码，生成与数据块对应的测试矢量。

公开(公告)号：US20090094307A1

公开(公告)日：2009-04-09

申请号：US11869022

申请日：2007-10-09

申请人： David N. Ault ,  Emiliano Lozano ,  Bao G. Truong ,  Samuel I. Ward

发明人： David N. Ault ,  Emiliano Lozano ,  Bao G. Truong ,  Samuel I. Ward

IPC分类号： G06F7/548

CPC分类号： G06F7/5446

摘要： Performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. Execution of the CORDIC algorithm is begun. An error introduced by a truncated vector as a result of executing the CORDIC algorithm is pre-computed. The error is incorporated into a subsequent iteration of the CORDIC algorithm. Execution of the CORDIC algorithm is completed. The result of the CORDIC algorithm is stored.

摘要翻译： 使用坐标旋转数字计算机（CORDIC）算法进行计算。 开始执行CORDIC算法。 作为执行CORDIC算法的结果的截断向量引入的​​误差是预先计算的。 该错误被并入CORDIC算法的后续迭代中。 完成CORDIC算法的执行。 存储CORDIC算法的结果。

公开(公告)号：US07468929B2

公开(公告)日：2008-12-23

申请号：US11609382

申请日：2006-12-12

申请人： Michael J. Lee ,  Bao G. Truong

发明人： Michael J. Lee ,  Bao G. Truong

IPC分类号： G11C5/14

CPC分类号： G11C7/22 ,  G11C11/413 ,  G11C2207/2227

摘要： A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed is provided. Logic is provided that identifies a polarity of a row of memory cells whose data values are to be read. The polarity of the row of memory cells indicates whether a majority of the data values stored in the row of memory cells are logic 1 data values or logic 0 data values. Based on the polarity, selection logic either selects true data values or complement data values of the memory cells. Additional logic is provided in each memory cell for outputting a true data value to a read bit line and outputting a compliment data value to the read bit line based on the polarity.

摘要翻译： 提供了当SRAM阵列被访问时减少SRAM阵列消耗的功率或能量的机构。 提供逻辑，其标识要读取其数据值的一行存储器单元的极性。 存储单元行的极性指示存储在存储单元行中的大部分数据值是逻辑1数据值还是逻辑0数据值。 基于极性，选择逻辑选择真实数据值或存储单元的补码数据值。 在每个存储器单元中提供附加的逻辑，用于将真实数据值输出到读位线，并且基于极性将补码数据值输出到读位线。

公开(公告)号：US20080137450A1

公开(公告)日：2008-06-12

申请号：US11609382

申请日：2006-12-12

申请人： Michael J. Lee ,  Bao G. Truong

发明人： Michael J. Lee ,  Bao G. Truong

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C11/413 ,  G11C2207/2227

摘要： A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed are provided. Logic is provided for determining the polarity of an incoming row being written to the SRAM cell array. Logic is further provided for storing a polarity value into an additional SRAM cell per row of the SRAM cell array. Logic is also provided for reading an inverted value of the SRAM cells of a row in the SRAM cell array if the row contains more 0's than 1's, as determined based on the polarity value stored in the additional SRAM cell per row. Logic is further provided for signaling to downstream logic whether the data read from the SRAM cells in the row represents the true data values or their complement, as determined based on the polarity value stored in the additional SRAM cell per row.

摘要翻译： 提供了当SRAM阵列被访问时减少SRAM阵列消耗的功率或能量的机构。 逻辑被提供用于确定被写入SRAM单元阵列的输入行的极性。 进一步提供逻辑用于将极性值存储到每个SRAM单元阵列的附加SRAM单元中。 如果根据存储在每行的附加SRAM单元中的极性值确定的行，如果该行包含多于0的逻辑，则还提供用于读取SRAM单元阵列中的行的SRAM单元的反相值的逻辑。 进一步提供逻辑用于向下游逻辑发信号，从行中的SRAM单元读取的数据是否基于存储在每行的附加SRAM单元中的极性值确定的真实数据值或其补码。

公开(公告)号：US20070283172A1

公开(公告)日：2007-12-06

申请号：US11420820

申请日：2006-05-30

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

IPC分类号： G06F1/00

CPC分类号： G06F1/26

摘要： A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.

摘要翻译： 提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。 感测单元感测电路的电压。 感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。 响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

公开(公告)号：US07208972B2

公开(公告)日：2007-04-24

申请号：US10845568

申请日：2004-05-13

申请人： Daniel M. Dreps ,  Anand Haridass ,  Bao G. Truong

发明人： Daniel M. Dreps ,  Anand Haridass ,  Bao G. Truong

IPC分类号： H03K17/16

CPC分类号： H04L25/061 ,  H04L25/45

摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.

摘要翻译： 两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。 产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。 导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。