公开(公告)号：US20090132971A1

公开(公告)日：2009-05-21

申请号：US12130040

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03B19/00 ,  G06F17/50

CPC分类号： G06F17/5045 ,  H03K3/017 ,  H03L7/0995 ,  H03L2207/06

摘要： A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

摘要翻译： 提供了一种用于在没有预定标器的情况下获得期望的锁相环（PLL）占空比的电路的设计结构。 说明性实施例的PLL电路利用在VCO上同时工作的两个单独的环路。 一个环路确保频率和相位锁定，而另一个环路确保占空比锁定。 VCO被修改为具有附加的控制端口来调整占空比。 因此，VCO具有用于执行频率调整的一个控制端口和用于占空比调整的一个控制端口。 结果，可以使用说明性实施例的PLL电路的VCO来控制占空比和频率，以便实现任何期望的占空比输出，而不需要VCO预定标器电路或占空比校正电路。

公开(公告)号：US07511554B2

公开(公告)日：2009-03-31

申请号：US11764262

申请日：2007-06-18

申请人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03L5/00

CPC分类号： H03K19/01812 ,  H03K19/01831

摘要： Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

摘要翻译： 在具有不同电源电压的域中的集成电路（IC）组件之间传送信号的系统和方法。 AC耦合用于增加信号的共模电压从一个电平转移到另一个电平的速度。 一个实施例包括用于电平移位IC中的二进制信号的方法。 该方法包括接收输入二进制信号并将其AC分量与其共模分量去耦。 第二共模分量被添加到AC分量，提供二进制输出信号。 输入信号的共模电压可以大于（或更小）输出信号的共模电压。 在该方法的一个实施例中，执行占空比补偿（DCC）。 DCC将占空比驱动到所需的值。

公开(公告)号：US20090021314A1

公开(公告)日：2009-01-22

申请号：US12128654

申请日：2008-05-29

申请人： David W. Boerstler ,  Nathaniel R. Chadwick ,  Eskinder Hailu ,  Kirk D. Peterson ,  Jieming Qi

发明人： David W. Boerstler ,  Nathaniel R. Chadwick ,  Eskinder Hailu ,  Kirk D. Peterson ,  Jieming Qi

IPC分类号： H03L1/02 ,  G05F1/567

CPC分类号： H03L1/022 ,  H03L1/04 ,  H03L7/0995

摘要： A design structure for an apparatus for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs, is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.

摘要翻译： 一种用于利用设置在集成电路器件，芯片等上的单组一个或多个热传感器（例如热二极管）的设备的设计结构，以控制集成电路器件，相关联的冷却系统和 提供高频PLL。 通过利用单组热传感器来提供多种功能，例如控制集成电路器件，冷却系统和PLL的操作，通过组合电路功能降低硅的不动产使用。 此外，通过降低电路复杂度并增加PLL对于温度的鲁棒性，可以提高集成电路器件的产量。 此外，通过补偿温度来提高PLL电路的工作范围。

公开(公告)号：US20090002038A1

公开(公告)日：2009-01-01

申请号：US11770867

申请日：2007-06-29

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03L7/085 ,  H03L7/08

CPC分类号： H03L7/18 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10

摘要： A hybrid phase locked loop (PLL) circuit for obtaining stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.

摘要翻译： 提供了用于获得稳定的动态响应和阻尼因子和环路带宽的独立调整的混合锁相环（PLL）电路。 说明性实施例的混合PLL电路包括常规RC PLL的电阻/电容（RC）滤波器元件以及从相位频率检测器的输出到压控振荡器（VCO）的前馈路径。 混合PLL本质上通过提供RC滤波器来增强常规前馈PLL的性能，RC滤波器的组件可以被加权，以提供对参数变化敏感性较低的动态响应，并且允许环路带宽优化而不牺牲阻尼。

公开(公告)号：US20080246524A1

公开(公告)日：2008-10-09

申请号：US12140335

申请日：2008-06-17

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

摘要翻译： 提供了一种占空比校正（DCC）电路，其中已知DCC电路拓扑中的成对的场效应晶体管（FET）被连接到DCC电路的开关的线性电阻器代替，使得当开关断开时，输入信号被路由 通过线性电阻。 线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。 线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。 线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

公开(公告)号：US07330061B2

公开(公告)日：2008-02-12

申请号：US11381050

申请日：2006-05-01

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K5/04

CPC分类号： H03K5/1565

摘要： The disclosed methodology and apparatus measure and correct the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds, thus providing a measured duty cycle. The apparatus generates an error signal when the measured duty cycle varies from a predetermined duty cycle. The apparatus includes a variable duty cycle clock generator that alters the duty cycle of the test clock signal to reduce the error.

摘要翻译： 所公开的方法和装置测量并校正时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。 在一个实施例中，DCM电路包括由电荷泵驱动的电容器。 参考时钟信号驱动电荷泵。 时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 控制软件访问数据存储器以确定测试时钟信号对应的占空比，从而提供测量的占空比。 当测量的占空比从预定的占空比变化时，该装置产生误差信号。 该装置包括可变占空比时钟发生器，其改变测试时钟信号的占空比以减少误差。

公开(公告)号：US07322001B2

公开(公告)日：2008-01-22

申请号：US11242677

申请日：2005-10-04

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R31/28 ,  H03K3/017

CPC分类号： H03K5/1565 ,  G01R31/31727 ,  G01R31/3187

摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance. A chip level built-in circuit automatically calibrates the duty cycle correction (DCC) circuit setting for each chip. The chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. A built-in self-test provides results, i.e. pass or fail, of an array to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.

摘要翻译： 一种用于自动校准占空比电路以实现最大性能的装置和方法。 芯片级内置电路自动校准每个芯片的占空比校正（DCC）电路设置。 芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。 内置的自检向DCC电路控制器提供阵列的结果，即通过或失败。 如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。 如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

公开(公告)号：US07200064B1

公开(公告)日：2007-04-03

申请号：US11246586

申请日：2005-10-07

申请人： David W. Boerstler ,  Eskinder Hailu ,  Subramanian Iyer ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Subramanian Iyer ,  Jieming Qi

IPC分类号： G11C7/00

CPC分类号： G11C17/18 ,  G11C17/16

摘要： An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming current sources and sensing current sources. When the pair of eFuses is to be programmed, a first programming current is applied to a first eFuse to thereby increase the resistance of the first eFuse by an incremental amount. When the pair of eFuses is to be returned to an unprogrammed state, a second programming current source is applied to a second eFuse to thereby increase a resistance of the second eFuse to be greater than the resistance of the first eFuse. When the sensing current is applied to the eFuses, a difference in the resulting voltages across the eFuses is identified and used to indicate whether the reprogrammable eFuse is in a programmed state or unprogrammed state.

摘要翻译： 提供了一种用于提供可再编程电可编程熔丝（eFuse）的设备和方法。 利用该装置和方法，提供一对耦合到编程电流源并感测电流源的eFuses。 当要对一对eFuse进行编程时，将第一编程电流施加到第一eFuse，从而增加第一eFuse的电阻增量。 当一对eFuse将返回到未编程状态时，第二编程电流源被施加到第二eFuse，从而将第二eFuse的电阻增加到大于第一eFuse的电阻。 当感应电流被施加到eFuse时，识别出eFuses上产生的电压的差异，并用于指示可重新编程的eFuse是否处于编程状态或未编程状态。

公开(公告)号：US08032850B2

公开(公告)日：2011-10-04

申请号：US12129945

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

IPC分类号： G06F17/50 ,  G01R23/00 ,  G01R29/26

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F2217/84

摘要： A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

摘要翻译： 提供了用于测量信号的绝对占空比的电路的设计结构。 选择来自信号源的非反相路径，并循环各种DCC电路设置索引，直到耦合到DCC电路的输出的分频器失效。 然后，基于故障时的DCC电路的指标值来确定分路器故障时的第一最小脉冲宽度。 选择来自信号源的反向路径，并且各种DCC电路设置索引再次循环，直到分频器失效。 然后，基于该第二次故障时的DCC电路的指标值来确定分路器故障时的第二最小脉冲宽度。 然后基于第一和第二最小脉冲宽度值的差来计算占空比。

公开(公告)号：US07958469B2

公开(公告)日：2011-06-07

申请号：US12128678

申请日：2008-05-29

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F17/50 ,  H03L7/085

CPC分类号： H03L7/099 ,  H03L7/093 ,  H03L7/183 ,  H03L2207/04

摘要： A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.

摘要翻译： 提供了一种用于获得稳定的动态响应和阻尼因子和环路带宽的独立调整的混合锁相环（PLL）电路的设计结构。 说明性实施例的混合PLL电路包括常规RC PLL的电阻/电容（RC）滤波器元件以及从相位频率检测器的输出到压控振荡器（VCO）的前馈路径。 混合PLL本质上通过提供RC滤波器来增强常规前馈PLL的性能，RC滤波器的组件可以被加权，以提供对参数变化敏感性较低的动态响应，并且允许环路带宽优化而不牺牲阻尼。