公开(公告)号：US08779529B2

公开(公告)日：2014-07-15

申请号：US13692369

申请日：2012-12-03

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L21/02

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US20120018816A1

公开(公告)日：2012-01-26

申请号：US12843350

申请日：2010-07-26

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US08076703B2

公开(公告)日：2011-12-13

申请号：US12603353

申请日：2009-10-21

Applicant: Akif Sultan ,  James F. Buller ,  Kaveri Mathur

Inventor： Akif Sultan ,  James F. Buller ,  Kaveri Mathur

IPC: H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

Abstract translation: 提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

公开(公告)号：US07504270B2

公开(公告)日：2009-03-17

申请号：US11425913

申请日：2006-06-22

Applicant: David D. Wu ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

Inventor： David D. Wu ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

IPC: G10R31/26 ,  H01L21/66

CPC classification number: H01L22/34 ,  G03F7/70658 ,  H01L22/12

Abstract: The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

Abstract translation: 本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构 表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果 以确定制造性角落四舍五入对多个测试结构的性能的影响。

公开(公告)号：US20070026599A1

公开(公告)日：2007-02-01

申请号：US11191684

申请日：2005-07-27

Applicant: Igor Peidous ,  Akif Sultan ,  Mario Pelella

Inventor： Igor Peidous ,  Akif Sultan ,  Mario Pelella

IPC: H01L21/8238 ,  H01L29/94

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: Methods are provided for fabricating a stressed MOS device. The method comprises the steps of forming a plurality of parallel MOS transistors in and on a semiconductor substrate. The parallel MOS transistors having a common source region, a common drain region, and a common gate electrode. A first trench is etched into the substrate in the common source region and a second trench is etched into the substrate in the common drain region. A stress inducing semiconductor material that has a crystal lattice mismatched with the semiconductor substrate is selectively grown in the first and second trenches. The growth of the stress inducing material creates both compressive longitudinal and tensile transverse stresses in the MOS device channel that enhance the drive current of P-channel MOS transistors. The decrease in drive current of N-channel MOS transistors caused by the compressive stress component is offset by the tensile stress component.

Abstract translation: 提供了制造应力MOS器件的方法。 该方法包括在半导体衬底中和半导体衬底上形成多个并联MOS晶体管的步骤。 并联MOS晶体管具有公共源极区，公共漏极区和公共栅电极。 第一沟槽被蚀刻到公共源极区域中的衬底中，并且第二沟槽被蚀刻到公共漏极区域中的衬底中。 在第一和第二沟槽中选择性地生长具有与半导体衬底失配的晶格的应力诱导半导体材料。 应力诱导材料的生长在MOS器件通道中产生压缩纵向和拉伸横向应力，从而增强P沟道MOS晶体管的驱动电流。 由压缩应力分量引起的N沟道MOS晶体管的驱动电流的减小由拉应力分量抵消。

公开(公告)号：US6087209A

公开(公告)日：2000-07-11

申请号：US126775

申请日：1998-07-31

Applicant: Geoffrey Choh-Fei Yeap ,  Akif Sultan ,  Shekhar Pramanick

Inventor： Geoffrey Choh-Fei Yeap ,  Akif Sultan ,  Shekhar Pramanick

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1079 ,  Y10S148/053

Abstract: Ultra shallow, low resistance LDD junctions are achieved by forming an LDD implant generating an interstitial-rich section and forming a sub-surface, non-amorphous region generating a vacancy-rich region substantially overlapping the interstitial rich region generated when forming the LDD implant. Embodiments include ion implanting, Ge or Si to form surface amorphous and sub-surface, non-amorphous regions, and implanting B or BF.sub.2 to form the impurity region. Embodiments include forming the sub-surface, non-amorphous region before or after generating the surface amorphous region, and forming the impurity region before or after forming the sub-surface, non-amorphous region but after forming the surface amorphous region.

Abstract translation: 通过形成LDD注入产生富含间隙的部分并形成基本上与形成LDD植入物时产生的间隙富集区域重叠的空位丰富区域的亚表面非非晶区域来实现超浅，低电阻LDD结。 实施例包括离子注入，Ge或Si以形成表面无定形和亚表面非非晶区域，以及注入B或BF 2以形成杂质区域。 实施例包括在产生表面无定形区域之前或之后形成子表面非非晶区域，以及在形成子表面非非晶区域之后或在形成表面无定形区域之后形成杂质区域。

公开(公告)号：US06008099A

公开(公告)日：1999-12-28

申请号：US50689

申请日：1998-03-30

Applicant: Akif Sultan ,  Dong-Hyuk Ju

Inventor： Akif Sultan ,  Dong-Hyuk Ju

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586

Abstract: A method of making a lightly doped drain transistor includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and forming a drain (70) in a drain region (58) and a source (72) in a source region (60) of the substrate (56). The method further includes generating interstitials (62) near a lateral edge of at least one of the drain (70) and the source (72) and thermally treating the substrate (56). The thermal treatment cause the interstitials (62) to enhance a lateral diffusion (84) of the drain (70) under the gate oxide (54) without substantially impacting a vertical diffusion (82) of the drain (70) or the source (72). The enhanced lateral diffusion (84) results in the formation of at least one of a lightly doped drain extension region (75) and a lightly doped source extension region (76) without an increase in a junction depth of the drain (70) or the source (72). The step of generating interstitials (62) may include the step of implanting at least one of the drain region (58) and the source region (60) of the substrate (56) with a large tilt angle implant which creates the interstitials (62) at a location near the gate oxide (54).

Abstract translation: 一种制造轻掺杂漏极晶体管的方法包括以下步骤：在半导体衬底（56）上形成栅电极（52）和栅极氧化物（54），并在漏区（58）中形成漏极（70） 源极（72）在衬底（56）的源极区（60）中。 所述方法还包括在所述排水口（70）和所述源（72）中的至少一个的侧边缘附近产生间隙（62）并热处理所述衬底（56）。 热处理使间隙（62）增强栅极氧化物（54）下面的漏极（70）的横向扩散（84），而基本上不影响漏极（70）或源极（72）的垂直扩散（82） ）。 增强的横向扩散（84）导致轻掺杂漏极延伸区域（75）和轻掺杂源极延伸区域（76）中的至少一个的形成，而不会增加漏极（70）或 来源（72）。 产生间隙（62）的步骤可以包括用产生间隙（62）的大倾斜角植入物植入衬底（56）的漏区（58）和源区（60）中的至少一个的步骤， 在栅极氧化物（54）附近。