公开(公告)号：US07515629B2

公开(公告)日：2009-04-07

申请号：US10390495

申请日：2003-03-17

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H04B1/38 ,  H04L5/16

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, either copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速位流接口模块包括线路侧接口，电路板侧接口和信号调理电路。 线路侧接口包括接收线路侧介质（铜介质或光介质）的介质耦合器。 板侧接口将高速串行比特流接口模块耦合到PCB。 信号调理电路通信耦合到线路侧接口和电路板侧接口。 信号调理电路从线路侧接口接收RX信号，对RX信号进行调节，并将接收信号提供给电路板侧接口。 信号调理电路从电路板侧接口接收TX信号，调节TX信号，并向板侧接口提供TX信号。

公开(公告)号：US20070182489A1

公开(公告)日：2007-08-09

申请号：US11695405

申请日：2007-04-02

Applicant: Ichiro Fujimori ,  Davide Tonietto

Inventor： Ichiro Fujimori ,  Davide Tonietto

IPC: H03G3/00

CPC classification number: H04B10/291

Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.

Abstract translation: 本发明的各方面可以提供用于调整多模PHY设备的输入信号的增益和/或频率响应的方法和系统。 信号分配器（704）可以在接收到输入信号时将输入信号分配成增益调整信号和/或均衡调整信号。 耦合到信号分配器（704）的信号调节器（702）可以调整多模PHY设备（130）内的分配增益调整信号的增益。 耦合到信号分配器（704）的均衡器（706）可以被配置为均衡多模PHY设备（130）内的均衡调整信号。 耦合到均衡器（706）和信号调节器（702）的加法器（708）可以适于将经调整的调整信号和多模PHY装置（130）内的均衡均衡调整信号相加，以产生输出均衡信号（712） 具有期望的增益和/或频率响应。

公开(公告)号：US20050271169A1

公开(公告)日：2005-12-08

申请号：US10880959

申请日：2004-06-30

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03G3/30 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L27/08

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract translation: 在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。 自动增益控制级可以包括具有可调节带宽的连续时间滤波器。 阈值调整信号可以应用于自动增益控制级的输出。 均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。