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    Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices
    31.
    发明授权
    Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices 失效
    用于通过绝缘体上硅（SOI）器件的掩埋互连实现覆盖的方法和半导体结构

    公开(公告)号：US06645796B2

    公开(公告)日：2003-11-11

    申请号：US09990477

    申请日：2001-11-21

    申请人： Todd Alan Christensen ,  John Edward Sheets, II

    发明人： Todd Alan Christensen ,  John Edward Sheets, II

    IPC分类号： H01L2100

    CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/78639

    摘要： A method and semiconductor structure including silicon-on-insulator (SOI) devices are provided for implementing reach through buried interconnect. A semiconductor stack includes a predefined buried conductor to be connected through multiple insulator layers and at least one intermediate conductor above the predefined buried conductor. A hole is anisotropically etched through the semiconductor stack to the predefined buried conductor. The etched hole extends through the at least one intermediate conductor and the insulators to the predefined buried conductor in the semiconductor stack. A thin layer of insulator is deposited over an interior of the etched hole. The deposited thin insulator layer is anisotropically etched to remove the deposited thin insulator layer from a bottom of the hole exposing the predefined buried conductor in the semiconductor stack with the thin insulator layer covering sidewalls of the hole to define an insulated opening. The insulated opening is filled with an interconnect conductor to create a connection to the predefined buried conductor in the semiconductor stack. A semiconductor structure for implementing reach through buried interconnect in building semiconductors including silicon-on-insulator (SOI) devices includes the semiconductor stack. An etched hole extends through at least one intermediate conductor and the insulators to the predefined buried conductor in the semiconductor stack. A thin layer of insulator covers sidewalls of the etched hole providing an insulated opening. An interconnect conductor extending through the insulated opening is connected to the predefined buried conductor in the semiconductor stack.

    摘要翻译： 提供了一种包括绝缘体上硅（SOI）器件的方法和半导体结构，用于通过掩埋互连实现覆盖。 半导体堆叠包括要通过多个绝缘体层连接的预定掩埋导体和在预定义掩埋导体上方的至少一个中间导体。 一个孔通过半导体堆叠被各向异性地蚀刻到预定义的掩埋导体。 蚀刻孔延伸穿过至少一个中间导体和绝缘体延伸到半导体叠层中的预定掩埋导体。 绝缘体的薄层沉积在蚀刻孔的内部。 沉积的薄绝缘体层被各向异性蚀刻以从沉积在半导体堆叠中的预定掩埋导体的孔的底部去除沉积的薄绝缘体层，薄绝缘体层覆盖孔的侧壁以限定绝缘开口。 绝缘开口填充有互连导体，以形成与半导体叠层中的预定掩埋导体的连接。 用于通过包括绝缘体上硅（SOI）器件在内的建筑半导体的掩埋互连实现覆盖的半导体结构包括半导体堆叠。 蚀刻孔延伸穿过至少一个中间导体，绝缘体延伸到半导体叠层中的预定掩埋导体。 绝缘体薄层覆盖蚀刻孔的侧壁，提供绝缘开口。 延伸穿过绝缘开口的互连导体连接到半导体叠层中的预定掩埋导体。

    Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test
    32.
    发明授权
    Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test 有权
    使用位线预充电应力操作来对存储单元进行测试的硅绝缘体SRAM存储单元的稳定性测试

    公开(公告)号：US06643804B1

    公开(公告)日：2003-11-04

    申请号：US09552410

    申请日：2000-04-19

    申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

    发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

    IPC分类号： G11C2900

    CPC分类号： G11C29/12 ,  G11C11/41 ,  G11C2029/1204

    摘要： An apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) introduce switching history effects to a memory cell during testing to stress the memory cell such that a reliable determination of stability may be made. Stress is applied to a memory cell through the use of a bitline precharge stress operation, which utilizes the bitline pairs coupled to a memory cell to attempt to flood the memory cell with charge and thereby attempt to cause the memory cell to unexpectedly switch state. The bitline precharge stress operation is performed immediately after the memory cell has been switched to one state after being maintained in an opposite state for a length of time that is sufficient to introduce switching history effects to the memory cell. While a bitline precharge operation may be implemented separate from any write operation, the bitline precharge stress operation may also be incorporated into a write operation through delaying the deassertion of the wordline that occurs in a conventional write operation until after initiation of the bitline precharge operation that conventionally occurs near the end of such a write operation.

    摘要翻译： 一种测试绝缘体上硅（SOI）静态随机存取存储器（SRAM）的装置，程序产品和方法在测试期间向存储器单元引入开关历史效应以对存储单元施加压力，从而稳定性的可靠确定可以是 制作。 通过使用位线预充电应力操作将应力施加到存储器单元，其利用耦合到存储器单元的位线对尝试以充电方式溢出存储器单元，从而尝试使存储器单元意外地切换状态。 在将存储单元切换到一个状态之后，立即执行位线预充电应力操作，并将其保持在相反的状态，持续足以将切换历史效应引入存储单元的时间长度。 尽管位线预充电操作可以与任何写操作分开实施，但是位线预充电应力操作也可以通过延迟在常规写操作中发生的字线的取消取消而被并入到写操作中，直到在开始位线预充电操作之后， 通常在这种写入操作的结束附近发生。

    Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips
    35.
    发明申请
    Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips 失效
    在集成电路芯片上实现热点热还原实现去耦电容

    公开(公告)号：US20100032799A1

    公开(公告)日：2010-02-11

    申请号：US12186837

    申请日：2008-08-06

    申请人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    发明人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0805

    摘要： A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.

    摘要翻译： 提供了一种方法和结构，用于在包括绝缘体上硅（SOI）电路的集成电路芯片上实现具有热点热还原的去耦电容器。 绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层以及由薄BOX层承载的有源层。 在有源层中的热点区域附近建立导热路径，以减少热效应，包括来自SOI结构背面的背面热连接。 背面热连接包括从SOI结构的背面延伸到硅衬底层的后侧蚀刻开口，形成在所述背面蚀刻开口上的电容器电介质; 以及沉积在填充所述背面蚀刻开口的所述电容器电介质上的热连接材料。

    Method and circuit for implementing enhanced LBIST testing of paths including arrays
    36.
    发明申请
    Method and circuit for implementing enhanced LBIST testing of paths including arrays 有权
    用于实现包括阵列的路径的增强型LBIST测试的方法和电路

    公开(公告)号：US20090183044A1

    公开(公告)日：2009-07-16

    申请号：US12015254

    申请日：2008-01-16

    申请人： Louis Bernard Bushard ,  Todd Alan Christensen ,  Jesse Daniel Smith

    发明人： Louis Bernard Bushard ,  Todd Alan Christensen ,  Jesse Daniel Smith

    IPC分类号： G01R31/3187 ,  G06F11/27

    CPC分类号： G01R31/3187

    摘要： A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

    摘要翻译： 一种包括存储器阵列和逻辑的电路路径的方法和电路实现测试，包括逻辑内置自测（LBIST）诊断，以及提供了主题电路所在的设计结构。 电路路径的测试包括用初始化模式初始化电路路径中的存储器阵列，切换到逻辑内置自测（LBIST）模式，并为存储器阵列提供只读模式，并运行逻辑内置自检（LBIST） ）测试电路路径。

    Split local and continuous bitline for fast domino read SRAM
    38.
    发明授权
    Split local and continuous bitline for fast domino read SRAM 有权
    分割本地和连续的位线快速多米诺骨牌SRAM

    公开(公告)号：US06657886B1

    公开(公告)日：2003-12-02

    申请号：US10140549

    申请日：2002-05-07

    申请人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger

    发明人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger

    IPC分类号： G11C1140

    CPC分类号： G11C11/419

    摘要： A high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality of SRAM cells and a local true bitline coupled to each of the plurality of SRAM cells of each local cell group. A continuous complement bitline is coupled to each of the plurality of local cell groups and is coupled to each of the plurality of SRAM cells of each local cell group. For a write to the SRAM cell complement node, only driving the continuous complement bitline is required. The domino SRAM reduces the number of required wires and required transistors as compared to prior art domino SRAM and thus the area needed and power consumption are reduced for the domino SRAM.

    摘要翻译： 提供了高性能的多米诺骨牌静态随机存取存储器（SRAM）。 多米诺SRAM包括多个本地小区组。 多个本地单元组中的每一个包括耦合到每个本地单元组的多个SRAM单元中的每一个的多个SRAM单元和本地真位线。 连续的补码位线耦合到多个局部单元组中的每一个，并耦合到每个本地单元组的多个SRAM单元中的每一个。 要写入SRAM单元补码节点，只需要驱动连续的补码位线。 与现有技术的多米诺骨牌SRAM相比，多米诺骨牌SRAM减少了所需的电线和所需的晶体管数量，因此为多米诺骨牌SRAM降低了所需的面积和功耗。

    Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices
    40.
    发明授权
    Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices 失效
    用于实现绝缘体（SOI）器件的埋地双轨配电和集成去耦电容的方法和半导体结构

    公开(公告)号：US06492244B1

    公开(公告)日：2002-12-10

    申请号：US09990478

    申请日：2001-11-21

    申请人： Todd Alan Christensen ,  John Edward Sheets, II

    发明人： Todd Alan Christensen ,  John Edward Sheets, II

    IPC分类号： H01L2176

    CPC分类号： H01L27/1203 ,  H01L21/76243

    摘要： Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers. A connection to the first intermediate silicon layer is formed without making electrical connection to the second intermediate silicon layer.

    摘要翻译： 提供了用于实现用于绝缘体上硅（SOI）器件的掩埋双轨配电和集成去耦电容的方法和半导体结构。 提供了限定一个配电轨的体硅衬底层。 执行高能深氧注入以产生深埋氧化层和第一中间硅层。 深埋氧化层设置在体硅衬底层和第一中间硅层之间。 第一中间硅层限定另一配电轨。 执行较低能量的氧注入以产生浅埋氧化物层和第二中间硅层。 浅埋氧化层设置在第一中间硅层和第二中间硅层之间。 形成与本体硅衬底层的连接，而不与中间硅层电连接。 形成与第一中间硅层的连接，而不与第二中间硅层电连接。