公开(公告)号：US08587338B1

公开(公告)日：2013-11-19

申请号：US13180932

申请日：2011-07-12

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G06F7/38

CPC分类号： H03K19/096 ,  G06F1/06

摘要： Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit includes a multiplexer and a logic module coupled to the multiplexer. The multiplexer is configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. The logic module includes at least one of an XNOR and an XOR module and is configured to provide an output signal that is responsive to performing at least one of an XNOR and an XOR operation of the output of the multiplexer and an enable signal that enables or disables the clock gate circuit to generate the clock signal.

公开(公告)号：US08407510B1

公开(公告)日：2013-03-26

申请号：US11546807

申请日：2006-10-11

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G06F1/04

CPC分类号： G11C7/1048 ,  G11C7/1066

摘要： Systems and techniques for improved bus control, which may be particularly useful for double data rate (DDR) data transfer. A circuit may include a clock transmitter in communication with a clock bus, a clock receiver in communication with the clock bus, and a driver in communication with the clock bus. The driver may drive a voltage of the clock bus to a first voltage level when the clock transmitter is not transmitting a clock signal on the clock bus and the clock receiver is not receiving a clock signal on the clock bus.

摘要翻译： 改进总线控制的系统和技术，可能对双数据速率（DDR）数据传输特别有用。 电路可以包括与时钟总线通信的时钟发射器，与时钟总线通信的时钟接收器以及与时钟总线通信的驱动器。 当时钟发送器不在时钟总线上发送时钟信号，时钟接收器没有在时钟总线上接收时钟信号时，驱动器可以将时钟总线的电压驱动到第一电压电平。

公开(公告)号：US08354857B1

公开(公告)日：2013-01-15

申请号：US12707142

申请日：2010-02-17

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G01R31/26 ,  G01R19/00

CPC分类号： G01R31/31725 ,  G01R31/3016

摘要： Aspects of the disclosure provide a speed monitor circuit. The speed monitor circuit monitors a circuit speed in a momentary manner. In addition, the speed monitor circuit consumes a relatively small silicon area. The speed monitor circuit includes a ring oscillator module, an edge capture module, and a controller module. The ring oscillator module has a plurality of stages, and is configured to start oscillating in response to an enable signal. The edge capture module is configured to capture a target edge of a signal propagating in the ring oscillator module at a stage of the ring oscillator module. The controller module is configured to receive a first edge and a second edge of a clock signal, provide the enable signal to the ring oscillator module based on the first edge to enable oscillating, and compare timings of the second edge and the captured target edge to detect the circuit speed.

摘要翻译： 本公开的方面提供了速度监视电路。 速度监控电路以瞬间的方式监视电路速度。 此外，速度监视器电路消耗相对较小的硅面积。 速度监视器电路包括环形振荡器模块，边缘捕获模块和控制器模块。 环形振荡器模块具有多个级，并且被配置为响应于使能信号开始振荡。 边缘捕获模块被配置为在环形振荡器模块的阶段捕获在环形振荡器模块中传播的信号的目标边缘。 控制器模块被配置为接收时钟信号的第一边缘和第二边缘，基于第一边缘向环形振荡器模块提供使能信号以使能振荡，并将第二边缘和捕获的目标边缘的定时与 检测电路速度。

公开(公告)号：US07948268B2

公开(公告)日：2011-05-24

申请号：US12882832

申请日：2010-09-15

申请人： Eitan Rosen ,  Dan Lieberman

发明人： Eitan Rosen ,  Dan Lieberman

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/00323 ,  H03K17/005

摘要： Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.

摘要翻译： 提供了多路复用器电路的时间平衡切换的方法和装置。 本发明的实施例包括耦合到多路复用器电路的输出的晶体管链。 晶体管链优选地延迟否则将相对快速地发生的转变，以匹配相对缓慢地发生的转变的定时。 相对较慢的转换的时间保持不变。 本发明有利地允许所有选择器输入转换以基本恒定的延迟产生数据输出转换。

公开(公告)号：US07808271B2

公开(公告)日：2010-10-05

申请号：US12405610

申请日：2009-03-17

申请人： Eitan Rosen ,  Dan Lieberman

发明人： Eitan Rosen ,  Dan Lieberman

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/00323 ,  H03K17/005

摘要： Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.

摘要翻译： 提供了多路复用器电路的时间平衡切换的方法和装置。 本发明的实施例包括耦合到多路复用器电路的输出的晶体管链。 晶体管链优选地延迟否则将相对快速地发生的转变，以匹配相对缓慢地发生的转变的定时。 相对较慢的转换的时间保持不变。 本发明有利地允许所有选择器输入转换以基本恒定的延迟产生数据输出转换。

公开(公告)号：US07743300B1

公开(公告)日：2010-06-22

申请号：US12291177

申请日：2008-11-06

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G01R31/28 ,  G06F11/00 ,  H03K19/00

CPC分类号： G01R31/31727

摘要： An integrated circuit includes a test signal generator that receives a clock signal including pulses having leading edges and trailing edges that occur at predetermined intervals and selectively generates a modified clock signal by adjusting timing of at least one of the leading and trailing edges of at least one of the pulses. A signal path includes a circuit and receives one of the clock signal and the modified clock signal from the test signal generator.

摘要翻译： 集成电路包括测试信号发生器，其接收包括具有以预定间隔发生的前沿和后沿的脉冲的时钟信号，并且通过调整至少一个的前沿和后沿中的至少一个来选择性地生成修改的时钟信号 的脉冲。 信号路径包括电路，并从测试信号发生器接收时钟信号和经修改的时钟信号之一。

公开(公告)号：US07461304B1

公开(公告)日：2008-12-02

申请号：US10614403

申请日：2003-07-07

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G11B20/20 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31727

摘要： An apparatus, method, and computer program for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the apparatus comprising a control circuit adapted to provide a control signal; and a signal generator adapted to receive a first clock signal comprising k pulses each having a first duration, change the duration of each of m of the pulses to a second duration in response to the control signal, wherein m

摘要翻译： 一种用于测试集成电路的装置，方法和计算机程序，所述集成电路包括多个具有时钟输入的时钟存储元件，其中所述计时存储元件通过多个信号路径互连，所述装置包括控制电路， 控制信号; 以及信号发生器，其适于接收包括每个具有第一持续时间的k个脉冲的第一时钟信号，以响应于所述控制信号将所述脉冲的每个m的持续时间改变为第二持续时间，其中m k和所述第二持续时间是 不等于第一持续时间，以产生第二时钟信号，并将第二时钟信号施加到多个计时存储元件的时钟输入端。

公开(公告)号：US07227398B2

公开(公告)日：2007-06-05

申请号：US11482562

申请日：2006-07-07

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： H03K3/00

CPC分类号： H03K3/0315 ,  H03K5/133 ,  H03L7/0812 ,  H03L7/0995

摘要： High resolution digital delay circuits and methods are provided. A multiplexer receives the outputs of first and second delay elements. At least the second delay element is adjustable using a digital control signal. The multiplexer and the first delay element form a first delay loop. The multiplexer, the first delay element and the second delay element form a second delay loop. A logic circuit monitors the number of times (M) that a signal cycles through the first loop. After M reaches a predetermined value (i.e., when the signal is delayed by a predetermined delay), the multiplexer receives a control signal that causes the second loop to close. A signal cycles through the second loop, which provides additional delay. Preferably, the signal cycles through the second loop only once. Generally, this causes the resolution of the delay circuit to be proportional to the minimum delay adjustment of the second delay element.

摘要翻译： 提供了高分辨率数字延迟电路和方法。 多路复用器接收第一和第二延迟元件的输出。 至少第二延迟元件可使用数字控制信号来调节。 多路复用器和第一延迟元件形成第一延迟环。 复用器，第一延迟元件和第二延迟元件形成第二延迟环。 逻辑电路监视信号循环通过第一个环路的次数（M）。 在M达到预定值之后（即，当信号被延迟预定的延迟）时，多路复用器接收使第二环路闭合的控制信号。 A信号循环通过第二个循环，这提供了额外的延迟。 优选地，信号仅循环通过第二循环一次。 通常，这导致延迟电路的分辨率与第二延迟元件的最小延迟调整成正比。

公开(公告)号：US07149139B1

公开(公告)日：2006-12-12

申请号：US10925641

申请日：2004-08-23

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G11C7/00

CPC分类号： G06F5/16 ,  G06F2205/065

摘要： Circuitry and methods for an efficient FIFO memory are provided. This efficient FIFO memory has two smaller standard single-port memory banks instead of one large dual-port memory bank, as in typical FIFO memories. Whereas the dual-port memory based FIFO memory can read and write data at the same time, a typical single-port memory based FIFO cannot. The operation of the two single-port memory banks are coordinated in order to provide similar or better performance than a dual-port memory based FIFO.

摘要翻译： 提供了有效的FIFO存储器的电路和方法。 这种高效的FIFO存储器具有两个较小的标准单端口存储器体组，而不是像典型的FIFO存储器那样的一个大的双端口存储器组。 而基于双端口存储器的FIFO存储器可以同时读取和写入数据，典型的基于单端口存储器的FIFO不能。 协调两个单端口存储器的操作，以提供与基于双端口存储器的FIFO类似或更好的性能。

公开(公告)号：US07126404B1

公开(公告)日：2006-10-24

申请号：US10973963

申请日：2004-10-25

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： H03K3/00

CPC分类号： H03K3/0315 ,  H03K5/133 ,  H03L7/0812 ,  H03L7/0995

摘要： High resolution digital delay circuits and methods are provided. A multiplexer receives the outputs of first and second delay elements. At least the second delay element is adjustable using a digital control signal. The multiplexer and the first delay element form a first delay loop. The multiplexer, the first delay element and the second delay element form a second delay loop. A logic circuit monitors the number of times (M) that a signal cycles through the first loop. After M reaches a predetermined value (i.e., when the signal is delayed by a predetermined delay), the multiplexer receives a control signal that causes the second loop to close. A signal cycles through the second loop, which provides additional delay. Preferably, the signal cycles through the second loop only once. Generally, this causes the resolution of the delay circuit to be proportional to the minimum delay adjustment of the second delay element.