公开(公告)号：US07876634B2

公开(公告)日：2011-01-25

申请号：US12085901

申请日：2005-12-02

申请人： David New ,  Paul Darren Hoxey ,  David Michael Bull ,  Shidhartha Das

发明人： David New ,  Paul Darren Hoxey ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G11C11/00

CPC分类号： G11C7/08 ,  G11C7/24 ,  G11C11/4125 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/26

摘要： A data processing system comprising a memory array having a plurality of memory cells and read circuitry for reading a logic value stored in one of the plurality of memory cells. The read circuitry is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.

摘要翻译： 一种数据处理系统，包括具有多个存储器单元的存储器阵列和用于读取存储在多个存储器单元之一中的逻辑值的读取电路。 读取电路可操作地执行存储的逻辑值的两个基本上同时的读取。 提供电压控制器并且可操作以选择性地改变对存储器阵列的电源电压的电平。 提供检测电路，用于根据两个基本上同时的读取来检测当电源电压电平导致读取结果不可靠时。

公开(公告)号：US07843760B2

公开(公告)日：2010-11-30

申请号：US12382428

申请日：2009-03-16

申请人： David Michael Bull ,  Shidhartha Das

发明人： David Michael Bull ,  Shidhartha Das

IPC分类号： G11C8/00

CPC分类号： G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1096 ,  G11C8/08

摘要： Interface circuitry is provided for coupling between a memory device and processing circuitry, the processing circuitry issuing a plurality of access signals relating to accesses to be performed in the memory device. The interface circuitry comprises write address latch circuitry for storing a write address signal, and write address decoder circuitry that is responsive to a set first enable signal to decode the write address signal provided from the write address latch circuitry. Further, read address latch circuitry is provided for storing a read address signal issued by the processing circuitry, and read address decoder circuitry is responsive to a set second enable signal for decoding the read address signal provided from the read address latch circuitry. Decoder select latch circuitry is responsive to an access type indication signal from the processing circuitry to generate the first and second enable signals in dependence on that access type indication signal. In the event of metastability occurring in the decoder select latch circuitry, the decoder select latch circuitry is arranged not to set at least the second enable signal, thereby disabling at least the read address decoder circuitry in the presence of such metastability. Such an approach prevents metastable signals being used in the arbitration of data accesses in a manner which could corrupt the state of the memory device.

摘要翻译： 提供接口电路用于在存储器件和处理电路之间耦合，处理电路发出与要在存储器件中执行的访问有关的多个访问信号。 接口电路包括用于存储写入地址信号的写入地址锁存电路，以及写入地址解码器电路，其响应于所设置的第一使能信号来解码从写入地址锁存电路提供的写入地址信号。 此外，提供读地址锁存电路用于存储由处理电路发出的读地址信号，并且读地址解码器电路响应于设置的第二使能信号，用于解码从读地址锁存电路提供的读地址信号。 解码器选择锁存电路响应来自处理电路的访问类型指示信号，以根据该访问类型指示信号产生第一和第二使能信号。 在解码器选择锁存电路发生亚稳定的情况下，解码器选择锁存电路被布置为不至少设置第二使能信号，从而在存在这种亚稳态的情况下至少禁用读地址解码器电路。 这种方法防止亚稳态信号以可能损坏存储器件的状态的方式在数据访问仲裁中使用。

公开(公告)号：US20100299557A1

公开(公告)日：2010-11-25

申请号：US12453835

申请日：2009-05-22

申请人： David Michael Bull ,  Shidhartha Das

发明人： David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/07

CPC分类号： G06F1/10 ,  G06F11/0757 ,  G06F11/0793

摘要： The application discloses a means of setting tuning limits for operational parameters in a processing stage within a data processing apparatus for processing a signal. The processing stage comprises: an input for receiving the signal, processing circuitry for processing the signal and an output for outputting the processed signal at an output time; an error detecting circuit for determining if a signal output by the processing stage between the output time and a predetermined time later does not have a stable value, the predetermined time later being before a next output time, and for signaling an error if the signal is not stable; a tuning circuit for adjusting at least one operational parameter of the processing stage; a tuning limiting circuit for providing at least one tuning limit for the tuning circuit, such that the at least one operational parameter is not adjusted beyond the corresponding at least one tuning limit, a tuning limiting circuit for providing at least one tuning limit for said tuning circuit, such that said at least one operational parameter is not adjusted beyond said corresponding at least one tuning limit, the tuning limiting circuit being configured to provide the at least one tuning limit such that a signal passing along a critical path of the processing stage tuned to the tuning limit is estimated to reach the output of the processing stage at a preset time later than the output time, the preset time being less than the predetermined time.

摘要翻译： 本申请公开了一种在处理信号的数据处理装置内的处理阶段中设置操作参数的调整极限的装置。 处理阶段包括：用于接收信号的输入，用于处理该信号的处理电路和用于在输出时输出处理的信号的输出; 用于确定在输出时间和预定时间之后由处理级输出的信号是否不具有稳定值的错误检测电路，之后的预定时间在下一个输出时间之前，并且如果信号是 不稳定 用于调整处理级的至少一个操作参数的调谐电路; 调谐限制电路，用于为调谐电路提供至少一个调谐极限，使得所述至少一个操作参数不被调整到相应的至少一个调谐极限之外;调谐限制电路，用于为所述调谐提供至少一个调谐极限 电路，使得所述至少一个操作参数不被调整超过所述对应的至少一个调谐极限，所述调谐限制电路被配置为提供所述至少一个调谐极限，使得沿着所述处理级的关键路径传递的信号被调谐 估计调谐极限在比输出时间晚的预设时间达到处理级的输出，预设时间小于预定时间。

公开(公告)号：US20100235697A1

公开(公告)日：2010-09-16

申请号：US12382427

申请日：2009-03-16

申请人： David Michael Bull ,  Shidhartha Das ,  David Theodore Blaauw

发明人： David Michael Bull ,  Shidhartha Das ,  David Theodore Blaauw

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177

摘要： An integrated circuit 2 is provided with domino logic including a speculative node 22 and a checker node 24. Precharged circuitry 36 precharges both the speculative node and the checker node. Logic circuitry 26 provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry 28, 30 first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry 26 have appropriate values. Error detection circuitry 32 detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.

摘要翻译： 集成电路2具有包括推测节点22和检验器节点24的多米诺逻辑逻辑。预充电电路36对推测节点和检验器节点进行预充电。 逻辑电路26根据输入信号值提供推测节点和校验器节点的放电路径。 评估控制电路28,30首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路26的输入信号具有适当的值，则它们可以被放电。 错误检测电路32在推测节点和检查器节点都不是放电的两者之一或两者未被充电时检测错误。

公开(公告)号：US20100232250A1

公开(公告)日：2010-09-16

申请号：US12382428

申请日：2009-03-16

申请人： David Michael Bull ,  Shidhartha Das

发明人： David Michael Bull ,  Shidhartha Das

IPC分类号： G11C8/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1096 ,  G11C8/08

摘要： Interface circuitry is provided for coupling between a memory device and processing circuitry, the processing circuitry issuing a plurality of access signals relating to accesses to be performed in the memory device. The interface circuitry comprises write address latch circuitry for storing a write address signal, and write address decoder circuitry that is responsive to a set first enable signal to decode the write address signal provided from the write address latch circuitry. Further, read address latch circuitry is provided for storing a read address signal issued by the processing circuitry, and read address decoder circuitry is responsive to a set second enable signal for decoding the read address signal provided from the read address latch circuitry. Decoder select latch circuitry is responsive to an access type indication signal from the processing circuitry to generate the first and second enable signals in dependence on that access type indication signal. In the event of metastability occurring in the decoder select latch circuitry, the decoder select latch circuitry is arranged not to set at least the second enable signal, thereby disabling at least the read address decoder circuitry in the presence of such metastability. Such an approach prevents metastable signals being used in the arbitration of data accesses in a manner which could corrupt the state of the memory device.

公开(公告)号：US20080250271A1

公开(公告)日：2008-10-09

申请号：US12076165

申请日：2008-03-14

申请人： Emre Ozer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Ozer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F11/07

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.

摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6刷新上游程序指令。 当多线程时，需要从指令流水线6清除来自包括作为错误恢复的结果而丢失的指令的线程的那些指令。 还可以根据诸如特权级别，依赖指令数量等的特性来选择指令。指令流水线可以附加地/替代地设置有与这些主存储器相关联的多个信号值的多于一个的主存储元件26,28 元件26,28以交替方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获与以下程序指令相对应的信号值。 这样可以避免冲洗。

公开(公告)号：US07320091B2

公开(公告)日：2008-01-15

申请号：US11110961

申请日：2005-04-21

申请人： David T. Blaauw ,  David Michael Bull ,  Shidhartha Das

发明人： David T. Blaauw ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/00

CPC分类号： G06F11/1695 ,  G06F9/3861 ,  G06F9/3869 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024。 非延迟信号捕获元件1016在非延迟捕获时间捕获来自处理逻辑1014的输出。 在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。 误差检测电路1026和误差校正电路1028检测并校正延迟值中的随机误差，并将错误检测的延迟值提供给比较器1024。 比较器1024比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获得太早，应该被错误检查的延迟值替换。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

公开(公告)号：US20070268755A1

公开(公告)日：2007-11-22

申请号：US11436983

申请日：2006-05-19

申请人： David New ,  Paul Darren Hoxey ,  David Michael Bull ,  Shidhartha Das

发明人： David New ,  Paul Darren Hoxey ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/12 ,  G11C29/1201 ,  G11C29/48 ,  G11C2207/108

摘要： A memory circuit is provided comprising a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit comprises a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is provided to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.

摘要翻译： 提供了一种存储器电路，其包括存储单元，一对导线，可操作用于发信号通知存储单元的逻辑状态，读取电路可操作以通过检测至少一对导线的电压来执行读操作。 存储器电路包括具有导通配置的下拉电路，其中其可操作以下拉一对导线中的至少一个导线的电压电平，以便影响读取操作，以及关断配置，其中 下拉电路不能影响读操作。 提供控制电路以控制下拉电路是处于接通配置还是断开配置。 存储器电路可以并入数据处理设备中，并且提供了一种操作存储器电路的方法，其中下拉电路被控制为处于接通配置或断开配置。

公开(公告)号：US07263015B2

公开(公告)日：2007-08-28

申请号：US11267574

申请日：2005-11-07

申请人： David Theodore Blaauw ,  David Michael Bull ,  Shidhartha Das

发明人： David Theodore Blaauw ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/418 ,  G11C8/08 ,  G11C8/10

摘要： A signal capture element for providing a first pre-charged logic level as first and second interim address portion signals during a pre-charged period and outputting during an evaluate period an address portion logic level as the first interim address portion signal and an inverted address portion logic level as the second interim address portion signal. First and second address portion signals are derivable respectively from first and second interim address portion signals. An inverter circuit for outputting to an address decoder during a pre-charged period a second pre-charged logic level as the first and second address portion signals. The inverter circuit having transfer characteristics that maintain voltage levels such that the first and second address portion signals are interpreted to be at the second pre-charged logic level despite the first or second interim address portion signal failing to transition to a valid logic level during the evaluate period.

摘要翻译： 一种信号捕捉元件，用于在预充电周期期间提供第一预充电逻辑电平作为第一和第二中间地址部分信号，并且在评估周期期间输出地址部分逻辑电平作为第一中间地址部分信号和反相地址部分 逻辑电平作为第二临时地址部分信号。 第一和第二地址部分信号可以分别从第一和第二临时地址部分信号导出。 一种逆变器电路，用于在预充电周期期间将作为第一和第二地址部分信号的第二预充电逻辑电平输出到地址译码器。 逆变器电路具有保持电压电平的传输特性，使得第一和第二地址部分信号被解释为处于第二预充电逻辑电平，尽管第一或第二临时地址部分信号在期间不能转换到有效逻辑电平 评估期

公开(公告)号：US08640008B2

公开(公告)日：2014-01-28

申请号：US13336428

申请日：2011-12-23

申请人： Guillaume Schon ,  Luca Scalabrino ,  Frederic Claude Marie Piry ,  David Michael Bull

发明人： Guillaume Schon ,  Luca Scalabrino ,  Frederic Claude Marie Piry ,  David Michael Bull

IPC分类号： H03M13/00

CPC分类号： G06F11/1407 ,  G06F11/1497

摘要： A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.

摘要翻译： 数据处理装置具有错误检测单元，每个错误检测单元被配置为如果与指令的执行相关联的信号的第一和第二采样不同，则生成错误信号。 错误值产生电路产生一个错误值，显示任何错误检测单元是否产生了错误信号。 误差值稳定电路执行稳定程序，包括重新采样误差值以消除亚稳态。 错误恢复电路如果错误值被确认则启动指令的重新执行。 计数电路与错误值相关联地保持计数器值，当误差值被产生并且每当在到达误差值稳定电路之前重新采样误差值时递减，计数器值被设置为预定值。 如果在错误值到达故障值稳定电路之前计数器值为零，则误差值会绕过稳定程序。