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公开(公告)号:US10971545B2
公开(公告)日:2021-04-06
申请号:US16245783
申请日:2019-01-11
Applicant: Everspin Technologies, Inc.
Inventor: Sanjeev Aggarwal , Kevin Conley , Sarin A. Deshpande
IPC: H01L27/22 , G11C5/06 , G11C5/08 , G11C11/16 , H01F10/32 , H01F41/34 , H01L21/768 , H01L23/522 , H01L23/528 , H01L43/02 , H01L43/12
Abstract: A magnetoresistive device may include multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers and electrically conductive vias extending through the one more dielectric material layers. Each MTJ stack may include multiple MTJ bits arranged one on top of another and the electrically conductive vias may be configured to electrically access each MTJ bit of the multiple MTJ stacks.
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公开(公告)号:US10777738B2
公开(公告)日:2020-09-15
申请号:US16576039
申请日:2019-09-19
Applicant: Everspin Technologies, Inc.
Inventor: Sanjeev Aggarwal , Sarin A. Deshpande , Kerry Joseph Nagel
Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
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公开(公告)号:US10541362B2
公开(公告)日:2020-01-21
申请号:US16380589
申请日:2019-04-10
Applicant: Everspin Technologies, Inc.
Inventor: Sarin A. Deshpande , Sanjeev Aggarwal , Moazzem Hossain
Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.
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公开(公告)号:US10535390B2
公开(公告)日:2020-01-14
申请号:US15831736
申请日:2017-12-05
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor: Sanjeev Aggarwal , Sarin A. Deshpande , Jon Slaughter
IPC: H01L29/82 , H01L21/8246 , H01L29/06 , H01L43/12 , H01L27/22 , B44C1/22 , G11B5/127 , H01L43/10 , G11C11/16 , H01L43/02
Abstract: The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. The method also may include performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon, wherein the sole annealing process is performed at a first minimum temperature. Subsequent to performing the sole annealing process, the method may include patterning or etching at least a portion of the magnetoresistive stack. Moreover, subsequent to the step of patterning or etching the portion of the magnetoresistive stack, the method may include performing all additional processing on the substrate at a second temperature below the first minimum temperature.
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35.
公开(公告)号:US10483460B2
公开(公告)日:2019-11-19
申请号:US15337123
申请日:2016-10-28
Applicant: Everspin Technologies, Inc.
Inventor: Kerry Joseph Nagel , Wenchin Lin , Sarin A. Deshpande , Jijun Sun , Sanjeev Aggarwal , Chaitanya Mudivarthi
Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching the first encapsulation layer which is disposed over the exposed surface of the dielectric layer. The method further includes (a) depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer and (b) depositing a third encapsulation layer: (i) on the second encapsulation layer which is on the first encapsulation layer and the exposed surface of the dielectric layer. The method also includes etching the remaining layers of the stack/structure (via one or more etch processes).
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公开(公告)号:US20190280045A1
公开(公告)日:2019-09-12
申请号:US16293729
申请日:2019-03-06
Applicant: Everspin Technologies, Inc.
Inventor: Sanjeev AGGARWAL , Kevin Conley , Sarin A. Deshpande
Abstract: A magnetoresistive device may include an annular-shaped magnetic tunnel junction (MTJ) bit having an inner end and an outer end. The MTJ bit may include an annular-shaped magnetically free region and an annular-shaped magnetically fixed region separated by an annular-shaped intermediate layer. A first electrical conductor may be in electrical contact with the inner end of the MTJ bit, and a second electrical conductor may be in electrical contact with the outer end of the MTJ bit.
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公开(公告)号:US10396279B2
公开(公告)日:2019-08-27
申请号:US16053072
申请日:2018-08-02
Applicant: Everspin Technologies, Inc.
Inventor: Sarin A. Deshpande , Sanjeev Aggarwal , Kerry Joseph Nagel
Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
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38.
公开(公告)号:US20190103554A1
公开(公告)日:2019-04-04
申请号:US16107543
申请日:2018-08-21
Applicant: Everspin Technologies, Inc.
Inventor: Sanjeev AGGARWAL , Sarin A. Deshpande , Kerry Joseph Nagel
IPC: H01L43/12
CPC classification number: H01L43/12 , H01L27/222 , H01L27/228
Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
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公开(公告)号:US10062839B2
公开(公告)日:2018-08-28
申请号:US15855984
申请日:2017-12-27
Applicant: Everspin Technologies, Inc.
Inventor: Sarin A. Deshpande , Sanjeev Aggarwal , Kerry Joseph Nagel
CPC classification number: H01L43/12 , G11B5/84 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
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40.
公开(公告)号:US20170125663A1
公开(公告)日:2017-05-04
申请号:US15337123
申请日:2016-10-28
Applicant: Everspin Technologies, Inc.
Inventor: Kerry Joseph Nagel , Wenchin Lin , Sarin A. Deshpande , Jijun Sun , Sanjeev Aggarwal , Chaitanya Mudivarthi
CPC classification number: H01L43/12 , G11C11/161 , G11C2211/5615 , H01L43/08
Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching the first encapsulation layer which is disposed over the exposed surface of the dielectric layer. The method further includes (a) depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer and (b) depositing a third encapsulation layer: (i) on the second encapsulation layer which is on the first encapsulation layer and the exposed surface of the dielectric layer. The method also includes etching the remaining layers of the stack/structure (via one or more etch processes).
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