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39 条记录 (耗时 0.036 秒)

    Data transfer between devices within an integrated circuit
    31.
    发明申请
    Data transfer between devices within an integrated circuit 有权
    集成电路内的器件之间的数据传输

    公开(公告)号：US20090210595A1

    公开(公告)日：2009-08-20

    申请号：US12320718

    申请日：2009-02-03

    申请人： Nicolas Chaussade

    发明人： Nicolas Chaussade

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4022 ,  H03M7/46

    摘要： An integrated circuit 2 is provided including multiple devices 4, 6, 8, 10, 12, 14 for communicating via an interconnect 16. A sending device 18 includes a sideband signal indicating the use of a representation of a repeating data word in place of that repeating data word itself. The receiving device can then form the repeating pattern of data words in response to receipt of the representation. This reduces the bandwidth consumed upon the interconnect 16.

    摘要翻译： 提供了集成电路2，其包括用于经由互连16进行通信的多个设备4,6,8,10,12,14。发送设备18包括表示使用重复数据字的表示的边带信号，代替该重复数据字的表示 重复数据字本身。 然后，响应于接收到表示，接收设备可以形成数据字的重复模式。 这减少了互连16上消耗的带宽。

    Control of access to a memory by a device
    32.
    发明授权
    Control of access to a memory by a device 有权
    控制设备对存储器的访问

    公开(公告)号：US07305534B2

    公开(公告)日：2007-12-04

    申请号：US10714561

    申请日：2003-11-17

    申请人： Simon Charles Watt ,  Lionel Belnet ,  David Hennah Mansell ,  Nicolas Chaussade ,  Peter Guy Middleton

    发明人： Simon Charles Watt ,  Lionel Belnet ,  David Hennah Mansell ,  Nicolas Chaussade ,  Peter Guy Middleton

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1491 ,  G06F21/6218 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2141 ,  G06F2221/2149

    摘要： The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the present invention, the data processing apparatus further comprises partition checking logic coupled to the device bus and operable whenever the memory access request as issued by the device pertains to the non-secure domain, to detect if the memory access request is seeking to access the secure memory and upon such detection to prevent the access specified by that memory request. This approach significantly improves the security of data contained within a secure portion of memory.

    摘要翻译： 本发明提供一种用于控制对存储器的访问的数据处理装置和方法。 数据处理装置具有安全域和非安全域，在安全域中，数据处理装置具有对非安全域中不可访问的安全数据的访问。 数据处理装置包括经由设备总线耦合到存储器的设备，并且当设备需要存储器中的数据项时，可以向设备总线发出存储器访问请求，该存储器访问请求涉及安全域或 非安全域。 存储器可操作以存储设备所需的数据，并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。 根据本发明，数据处理装置还包括耦合到设备总线的分区检查逻辑，每当由设备发布的存储器访问请求与非安全域相关时，可操作，以检测存储器访问请求是否正在寻找 以访问安全存储器并且在这种检测时防止由该存储器请求指定的访问。 这种方法显着提高了包含在存储器安全部分内的数据的安全性。

    Vectored interrupt control within a system having a secure domain and a non-secure domain
    34.
    发明授权
    Vectored interrupt control within a system having a secure domain and a non-secure domain 有权
    具有安全域和非安全域的系统内的向量中断控制

    公开(公告)号：US07117284B2

    公开(公告)日：2006-10-03

    申请号：US10714562

    申请日：2003-11-17

    申请人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Jonathan Sean Callan

    发明人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Jonathan Sean Callan

    IPC分类号： G06F13/24

    CPC分类号： G06F9/4812

    摘要： A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.

    摘要翻译： 数据处理装置可以以多种模式操作，也可以在安全域或非安全域中操作。 当在安全域内以安全模式操作时，程序可以访问当处理器以非安全模式操作时无法访问的安全数据。 提供向量中断控制器以响应于发生除了条件而产生异常处理程序地址。 向量中断控制器是可编程的，参数指定每个异常情况是否应触发安全或非安全域中的异常处理程序，如果在适当的域中发生异常，则使用异常处理程序地址。 向量中断控制器还包括指定域切换异常处理程序地址的参数，以便在处理器不在适当域中时发生异常情况时使用。

    Data transfer between devices within an integrated circuit
    35.
    发明授权
    Data transfer between devices within an integrated circuit 有权
    集成电路内的器件之间的数据传输

    公开(公告)号：US07934029B2

    公开(公告)日：2011-04-26

    申请号：US12320718

    申请日：2009-02-03

    申请人： Nicolas Chaussade

    发明人： Nicolas Chaussade

    IPC分类号： G06F13/12 ,  H03M7/38

    CPC分类号： G06F13/4022 ,  H03M7/46

    摘要： An integrated circuit 2 is provided including multiple devices 4, 6, 8, 10, 12, 14 for communicating via an interconnect 16. A sending device 18 includes a sideband signal indicating the use of a representation of a repeating data word in place of that repeating data word itself. The receiving device can then form the repeating pattern of data words in response to receipt of the representation. This reduces the bandwidth consumed upon the interconnect 16.

    摘要翻译： 提供了集成电路2，其包括用于经由互连16进行通信的多个设备4,6,8,10,12,14。发送设备18包括表示使用重复数据字的表示的边带信号，代替该重复数据字的表示 重复数据字本身。 然后，响应于接收到表示，接收设备可以形成数据字的重复模式。 这减少了互连16上消耗的带宽。

    Exception types within a secure processing system
    37.
    发明申请
    Exception types within a secure processing system 有权
    安全处理系统中的异常类型

    公开(公告)号：US20090259846A1

    公开(公告)日：2009-10-15

    申请号：US12382647

    申请日：2009-03-20

    申请人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephanie Eric Sebastien Brochier

    发明人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephanie Eric Sebastien Brochier

    IPC分类号： H04L9/00

    CPC分类号： G06F21/74 ,  G06F9/4812 ,  G06F2209/481

    摘要： An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

    摘要翻译： 一种用于处理数据的装置包括可以以多种模式操作的处理器，包括至少一种安全模式，即安全域中的模式，以及至少一种非安全模式是非安全域中的模式。 当处理器以安全模式执行程序时，程序可以访问当处理器以非安全模式运行时无法访问的安全数据。 处理器响应于一个或多个异常条件，以使用异常处理程序触发异常处理。 处理器可操作以依赖于处理器是否在安全域或非安全域中操作从多个可能的异常处理程序中选择异常处理程序。

    Data transfer between a master and slave
    39.
    发明申请
    Data transfer between a master and slave 有权
    主机与从机之间的数据传输

    公开(公告)号：US20080147921A1

    公开(公告)日：2008-06-19

    申请号：US11979361

    申请日：2007-11-01

    申请人： Nicolas Chaussade ,  Pierre Michel Broyer ,  Phillipe Luc

    发明人： Nicolas Chaussade ,  Pierre Michel Broyer ,  Phillipe Luc

    IPC分类号： G06F1/12

    CPC分类号： G06F13/4291

    摘要： A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configured to output signals that are different to each other.

    摘要翻译： 一种数据处理装置，包括至少一个启动器，其可操作以经由总线与至少一个接收者通信; 所述至少一个起动器包括用于向所述总线发送数据的输出端口和用于从所述总线接收数据的输入端口; 所述数据处理装置还包括启动器时钟信号发生器，启动器输出使能信号发生器和启动器输入使能信号发生器，所述启动器由所述启动器时钟信号计时; 所述输出端口由所述启动器输出使能信号计时，使得所述输出端口可操作以响应于具有第一预定电平的所述启动器输出使能信号而将数据断言在所述总线上的写通道，并且所述输入端口可操作以锁存数据 响应于所述启动器输入使能信号具有第二预定电平，在所述总线上的读通道上接收; 其中所述启动器输出使能信号发生器和启动器输入使能信号发生器被配置为输出彼此不同的信号。