公开(公告)号：US20110090748A1

公开(公告)日：2011-04-21

申请号：US12907746

申请日：2010-10-19

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C7/10

CPC classification number: G11C5/145 ,  G11C7/00 ,  G11C7/10 ,  G11C16/06 ,  G11C16/14

Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.

Abstract translation: 本公开涉及一种用于向至少一个集成电路提供用于擦除和/或编程存储器的高电压的装置。 该装置包括与集成电路的至少一个接触端子相连的至少一个接触端子，用于监视由集成电路接收的数据信号并在数据信号中检测存储器的写入命令的监视器，以及用于 当监视器检测到存储器的写入命令时，将高电压施加到集成电路的端子。

公开(公告)号：US07868392B2

公开(公告)日：2011-01-11

申请号：US11172609

申请日：2005-06-30

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H01L29/76

CPC classification number: H01L27/0921 ,  H01L21/8238

Abstract: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RP−, RP−) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN−, RP−) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).

Abstract translation: 集成电路，包括形成在衬底（1,2）中的掺杂区（3至8），形成具有两个寄生双极晶体管（T1，T2）的寄生晶闸管结构，所述集成电路包括两个互连的金属化（16,19） 集成电路的两个对应的掺杂区域（4,5,6,7），以便降低两个双极晶体管的基极电阻（RN-，RP-），至少一个金属化层（16,19）被执行到 将两个双极晶体管的基极电阻（RN-，RP-）整体通过衬底（1,2）连接到集成电路中的电源金属化（15,16）。

公开(公告)号：US07714622B2

公开(公告)日：2010-05-11

申请号：US11624135

申请日：2007-01-17

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H03K5/153

CPC classification number: H03K5/086

Abstract: An input stage of an integrated circuit, includes a comparator for comparing the voltage of an input signal of the input stage with a reference voltage, and supplying a binary output signal the value of which depends on the result of the comparison of the input signal with the reference voltage. The input stage comprises a feedback circuit measuring a parameter representative of the operation of the comparator, and raising the reference voltage while the measured parameter reveals a faulty operation of the comparator.

Abstract translation: 集成电路的输入级包括比较器，用于将输入级的输入信号的电压与参考电压进行比较，并提供二进制输出信号，该二进制输出信号的值取决于输入信号的比较结果与 参考电压。 输入级包括测量表示比较器的操作的参数的反馈电路，以及提高参考电压，而测量的参数显示比较器的故障操作。

公开(公告)号：US20100110791A1

公开(公告)日：2010-05-06

申请号：US12613341

申请日：2009-11-05

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/0425 ,  G11C16/08 ,  G11C16/26

Abstract: The disclosure relates to an electrically erasable and programmable memory, comprising memory cells arranged in bit lines and word lines transverse to bit lines, wherein each memory cell may be in a programmed or erased state, the memory comprising memory cell selection circuits configured to memorize and read data bits in two memory cells belonging to different bit lines and different word lines, and to avoid a memory cell from being written or read by mistake in another state than a default state after a gate oxide breakdown of a transistor of the memory, and a read circuit to determine a data bit to be read in the memory according to the states of the two memory cells memorizing the data bit.

Abstract translation: 本公开涉及一种电可擦除和可编程存储器，其包括以位线和横向于位线的字线布置的存储器单元，其中每个存储器单元可以处于编程或擦除状态，所述存储器包括存储器单元选择电路，其被配置为存储和 在属于不同位线和不同字线的两个存储单元中读取数据位，并且避免存储器单元在存储器的晶体管的栅极氧化物击穿之后的另一状态下被错误地写入或读取，而不是默认状态;以及 读取电路，用于根据存储数据位的两个存储单元的状态来确定要在存储器中读取的数据位。

公开(公告)号：US20070188961A1

公开(公告)日：2007-08-16

申请号：US11626086

申请日：2007-01-23

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H02H3/00

CPC classification number: H01L27/0266 ,  H01L27/0921

Abstract: Device for protecting an integrated circuit, comprising a device for detecting a latch-up condition, and a supply voltage control device for controlling a supply voltage of the integrated circuit, to modify a parameter of the supply voltage of the integrated circuit in order to prevent the latch-up from becoming permanently established.

Abstract translation: 用于保护集成电路的装置，包括用于检测闩锁状态的装置，以及用于控制集成电路的电源电压的电源电压控制装置，以修改集成电路的电源电压的参数，以防止 闩锁从永久建立。

公开(公告)号：US20070164795A1

公开(公告)日：2007-07-19

申请号：US11624135

申请日：2007-01-17

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H03B1/00

CPC classification number: H03K5/086

Abstract: An input stage of an integrated circuit, includes a comparator for comparing the voltage of an input signal of the input stage with a reference voltage, and supplying a binary output signal the value of which depends on the result of the comparison of the input signal with the reference voltage. The input stage comprises a feedback circuit measuring a parameter representative of the operation of the comparator, and raising the reference voltage while the measured parameter reveals a faulty operation of the comparator.

Abstract translation: 集成电路的输入级包括比较器，用于将输入级的输入信号的电压与参考电压进行比较，并提供二进制输出信号，该二进制输出信号的值取决于输入信号的比较结果与 参考电压。 输入级包括测量表示比较器的操作的参数的反馈电路，以及提高参考电压，而测量的参数显示比较器的故障操作。

公开(公告)号：US5016078A

公开(公告)日：1991-05-14

申请号：US551555

申请日：1990-07-11

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0259

Abstract: The disclosure concerns integrated circuits and, more particularly, their protection against electrostatic discharges. To protect a metallized pad in a CMOS circuit on an N substrate with P wells, an NPN type lateral bipolar transistor formed in a P-type well is used. The emitter is an N+ region connected to the pad. The collector is an N+ region connected to a metallization which is itself connected, like the substrate N, to the high supply voltage Vcc of the circuit. The well is taken to the potential of the pad to be protected by means of an ohmic contact by a P+ surface diffusion of the well. In the preferred embodiment of the invention, the region that acts as a collector includes a part extending laterally outside the P well, and it is in this external part that the contact with the metallization occurs. The contact is at a sufficient distance from the well for there to be no risk of damage to the trench/substrate junction when the density of current flowing through the metallization is high.

Abstract translation: 本公开涉及集成电路，更具体地涉及它们对静电放电的保护。 为了保护具有P阱的N衬底上的CMOS电路中的金属化焊盘，使用在P型阱中形成的NPN型横向双极晶体管。 发射极是连接到焊盘的N +区域。 集电极是连接到金属化的N +区域，其自身像衬底N一样连接到电路的高电源电压Vcc。 通过阱的P +表面扩散，通过欧姆接触将阱吸收到衬垫的电位。 在本发明的优选实施例中，用作集电器的区域包括在P阱的横向外侧延伸的部分，并且在该外部部分中发生与金属化的接触。 接触距井的距离足够远，当流过金属化的电流密度高时，不存在损坏沟槽/衬底结的风险。

公开(公告)号：US08994022B2

公开(公告)日：2015-03-31

申请号：US13443778

申请日：2012-04-10

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H01L29/788 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.

Abstract translation: 本公开的实施例涉及一种评估半导体晶片切割工艺的方法，包括提供在晶片的至少一个划线中延伸的评估线，在划线中切割晶片，评估评估线的长度，提供信息 关于他们的长度，并使用信息来评估切片过程。

公开(公告)号：US20130064014A1

公开(公告)日：2013-03-14

申请号：US13610425

申请日：2012-09-11

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: G11C16/04

CPC classification number: G11C16/0425 ,  G11C16/08

Abstract: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.

Abstract translation: 本公开涉及一种电可擦除和可编程存储器，其包括与第一和第二控制栅极晶体管并联的至少一个存储单元字，以将控制栅极电压施加到该字的存储单元。 存储器还包括通过第一限流器向第一控制栅极晶体管的控制端提供第一控制电压的第一控制电路，以及向第二控制栅极的控制端提供第二控制电压的第二控制电路 晶体管通过第二限流器。

公开(公告)号：US20130051153A1

公开(公告)日：2013-02-28

申请号：US13599222

申请日：2012-08-30

Applicant: Francois Tailliet ,  Yvon Bahout

Inventor： Francois Tailliet ,  Yvon Bahout

IPC: G11C16/04

CPC classification number: G11C7/1018 ,  G11C8/12

Abstract: A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row i is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

Abstract translation: 一种用于电气编程非易失性存储器的方法，其中编程周期包括对应于存储器平面的第一行和列的初始地址的存储器单元的先前寻址。 该方法可以包括在达到第一行i的末端时在第二个连续行中寻址存储单元，以将数据存储在具有连续和增加地址的位在两个连续的行中。