公开(公告)号：US08779551B2

公开(公告)日：2014-07-15

申请号：US13489537

申请日：2012-06-06

申请人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

发明人： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

IPC分类号： H01L27/06

CPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

摘要翻译： 一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻 其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

公开(公告)号：US08299519B2

公开(公告)日：2012-10-30

申请号：US12685335

申请日：2010-01-11

申请人： Anthony I. Chou ,  Arvind Kumar

发明人： Anthony I. Chou ,  Arvind Kumar

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11558 ,  H01L29/1087 ,  H01L29/78615

摘要： A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

摘要翻译： 提供了一种用于使用身体接触的SOI晶体管的单个多重非易失性存储器的读取晶体管及其制造方法。 非易失性随机存取存储器形成在绝缘体上硅（SOI）中。 非易失性随机存取存储器包括在SOI的硅中形成有体接触的读取场效应晶体管（FET）。 身体接触与读取FET的栅极下方的扩散区域电接触。

公开(公告)号：US20110169064A1

公开(公告)日：2011-07-14

申请号：US12685335

申请日：2010-01-11

申请人： Anthony I. Chou ,  Arvind Kumar

发明人： Anthony I. Chou ,  Arvind Kumar

IPC分类号： H01L29/94 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11558 ,  H01L29/1087 ,  H01L29/78615

摘要： A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

摘要翻译： 提供了一种用于使用身体接触的SOI晶体管的单个多重非易失性存储器的读取晶体管及其制造方法。 非易失性随机存取存储器形成在绝缘体上硅（SOI）中。 非易失性随机存取存储器包括在SOI的硅中形成有体接触的读取场效应晶体管（FET）。 身体接触与读取FET的栅极下方的扩散区域电接触。

公开(公告)号：US07956415B2

公开(公告)日：2011-06-07

申请号：US12133686

申请日：2008-06-05

申请人： Anthony I. Chou ,  Andres Bryant ,  Arvind Kumar ,  Shreesh Narasimha

发明人： Anthony I. Chou ,  Andres Bryant ,  Arvind Kumar ,  Shreesh Narasimha

IPC分类号： H01L27/12

CPC分类号： H01L29/66772 ,  H01L29/78603 ,  H01L29/78612

摘要： A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.

摘要翻译： 顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。 身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。 任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。

公开(公告)号：US20090315138A1

公开(公告)日：2009-12-24

申请号：US12141276

申请日：2008-06-18

申请人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L27/12 ,  H01L21/3205

CPC分类号： H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.

摘要翻译： 在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。

公开(公告)号：US08232599B2

公开(公告)日：2012-07-31

申请号：US12683456

申请日：2010-01-07

申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/1207 ,  H01L21/84

摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US20120187492A1

公开(公告)日：2012-07-26

申请号：US13425681

申请日：2012-03-21

申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC分类号： H01L27/088

CPC分类号： H01L27/1207 ,  H01L21/84

摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US08173524B1

公开(公告)日：2012-05-08

申请号：US13004201

申请日：2011-01-11

申请人： Ashima B. Chakravarti ,  Anthony I. Chou ,  Abhishek Dube ,  Dominic J. Schepis

发明人： Ashima B. Chakravarti ,  Anthony I. Chou ,  Abhishek Dube ,  Dominic J. Schepis

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/165 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02639 ,  H01L29/78 ,  H01L29/7848

摘要： Methods form epitaxial materials by forming at least two gate stacks on a silicon substrate and forming sidewall spacers on sides of the gate stacks. Such methods pattern a recess in the silicon substrate between adjacent ones of the gate stacks. The methods also provide a liner in a bottom of the recess, and epitaxially grow epitaxial material from sidewalls of the recess to fill the recess with the epitaxial material.

摘要翻译： 方法通过在硅衬底上形成至少两个栅极叠层并在栅叠层的侧面上形成侧壁间隔来形成外延材料。 这种方法在相邻的栅叠层之间的硅衬底中形成凹陷。 该方法还在凹槽的底部提供衬垫，并且从凹槽的侧壁外延生长外延材料，以用外延材料填充凹部。

公开(公告)号：US07814454B2

公开(公告)日：2010-10-12

申请号：US11770303

申请日：2007-06-28

申请人： Anthony I. Chou ,  James S. Dunn ,  Brian M. Dufrene ,  Christopher H. Lumbra ,  Shreesh Narasimha ,  Christopher S. Putnam ,  BethAnn Rainey ,  Christopher M. Schnabel

发明人： Anthony I. Chou ,  James S. Dunn ,  Brian M. Dufrene ,  Christopher H. Lumbra ,  Shreesh Narasimha ,  Christopher S. Putnam ,  BethAnn Rainey ,  Christopher M. Schnabel

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.

摘要翻译： 一种允许多个设备放置在焊盘之间的系统，方法和程序产品，使得后端（BEOL）掩模更改可用于选择不同的设备选项。 公开了一种用于实现用于表征集成电路技术中的器件的测试现场的系统，并且包括：用于为一组芯片焊盘设计多个器件选项的系统; 用于为所述多个设备选项中的每一个设计伪布线布局的系统; 用于选择所述设备选项之一的系统; 用于将所选择的设备选项的伪布线布局映射到预定设计级的系统; 以及用于在具有针对所选择的设备选项映射的布线布局的预定设计级别处输出配置的掩模设计的系统。

公开(公告)号：US20090269926A1

公开(公告)日：2009-10-29

申请号：US12110594

申请日：2008-04-28

申请人： Abhishek Dube ,  Ashima B. Chakravarti ,  Anthony I. Chou ,  Wei He ,  Dominic J. Schepis

发明人： Abhishek Dube ,  Ashima B. Chakravarti ,  Anthony I. Chou ,  Wei He ,  Dominic J. Schepis

IPC分类号： H01L21/44

CPC分类号： H01L21/28035 ,  H01L29/4925

摘要： A method of forming at least one gate conductor of a complementary metal oxide semiconductor performs a chemical vapor deposition process of polysilicon over a surface where a polysilicon gate is to be located. This deposition can be performed through a mask to form gate structures directly, or a later patterning process can pattern the polysilicon into gate structures. During the chemical vapor deposition process, the method adds impurities in the chemical vapor deposition process to optimize the grain size of the polysilicon according to a number of different methods.

摘要翻译： 形成互补金属氧化物半导体的至少一个栅极导体的方法在多晶硅栅极位于的表面上进行多晶硅的化学气相沉积处理。 该沉积可以通过掩模进行直接形成栅极结构，或者后来的图案化工艺可以将多晶硅图案化成栅极结构。 在化学气相沉积过程中，该方法根据多种不同的方法在化学气相沉积工艺中添加杂质以优化多晶硅的晶粒尺寸。