公开(公告)号：US08987858B2

公开(公告)日：2015-03-24

申请号：US13846380

申请日：2013-03-18

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Stephen Daley Arthur

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/861

CPC classification number: H01L29/1608 ,  H01L21/0445 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/265 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/32 ,  H01L29/6606 ,  H01L29/8618 ,  H01L2924/10272

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract translation: 提供瞬态电压抑制（TVS）装置和形成装置的方法。 该器件包括由第一导电类型材料形成的第一层宽带隙半导体材料，在第一层的至少一部分上由第二导电类型材料形成的第二层宽带隙半导体材料，并且包括离子注入 材料结构在0.1微米（μm）和22.0μm厚之间，第二层使用穿透物理学操作，以及在第二层的至少一部分上由第一导电类型材料形成的第三层宽带隙半导体材料。

公开(公告)号：US20140159141A1

公开(公告)日：2014-06-12

申请号：US13712188

申请日：2012-12-12

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.

Abstract translation: 绝缘栅场效应晶体管（IGFET）器件包括半导体本体和栅极氧化物。 半导体本体包括掺杂有第一类型掺杂剂的第一阱区域和掺杂有相反电荷的第二类型掺杂剂并位于第一阱区域内的第二阱区域。 栅极氧化物包括具有不同厚度尺寸的外部部分和内部部分。 外部部分设置在半导体本体的第一阱区域和第二阱区域的上方。 内部部分设置在半导体本体的结栅场效应晶体管区域的上方。 半导体本体被配置为当栅极信号施加到设置在栅极氧化物上的栅极触点时，通过第二阱区域和结栅场效应晶体管区域形成导电沟道。