公开(公告)号：US11121023B2

公开(公告)日：2021-09-14

申请号：US16548192

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Hong Yu ,  Jinping Liu ,  Hui Zang

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A finFET device is disclosed including a fin defined in a semiconductor substrate, the fin having an upper surface and a first diffusion break positioned in the fin, wherein the first diffusion break comprises an upper surface that is substantially coplanar with the upper surface of the fin.

公开(公告)号：US11094598B2

公开(公告)日：2021-08-17

申请号：US16508815

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Bharat V. Krishnan ,  Rinus Tek Po Lee ,  Jiehui Shu ,  Hyung Yoon Choi

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/67 ,  H01L29/49

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.

公开(公告)号：US20210233934A1

公开(公告)日：2021-07-29

申请号：US16774087

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

公开(公告)号：US20210183997A1

公开(公告)日：2021-06-17

申请号：US17185236

申请日：2021-02-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Hui Zang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/764 ,  H01L21/768

Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.

公开(公告)号：US10923469B2

公开(公告)日：2021-02-16

申请号：US16244169

申请日：2019-01-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hui Zang ,  Guowei Xu ,  Jiehui Shu ,  Ruilong Xie ,  Yurong Wen ,  Garo J. Derderian ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L27/06 ,  H01L29/66 ,  H01L49/02 ,  H01L21/762 ,  H01L23/522 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.