公开(公告)号：US08473569B2

公开(公告)日：2013-06-25

申请号：US11060946

申请日：2005-02-18

Applicant: Bradley K. Lane ,  Lisa A. Ferrera ,  Pascal Dorster ,  Timothy A. Adcock ,  Gene A. Frantz

Inventor： Bradley K. Lane ,  Lisa A. Ferrera ,  Pascal Dorster ,  Timothy A. Adcock ,  Gene A. Frantz

IPC: G06F15/16

CPC classification number: G06F9/5044 ,  G06F2209/509 ,  H04L67/08

Abstract: In order to provide a home user with cost-effective PC processing capability, the home user is provided with a terminal which has only sufficient processing capability to communicate with a service provider over a network. Any processing and program execution is performed, in response to requests from the home user's terminal, by the service provider and the results are returned to the terminal. In addition to the processing capability, data is stored in the service provider. Because the processing and data storage is performed by the service provider, changes to the programs and/or hardware can the confined to the processing resources of the service provider. In addition, the service provider can be provided with virus and hacking protection, protection that will then not be necessary for the home user's terminal. In this manner, the home user can be charged for only the facilities and software that are actually used, while having available the full capability of a personal computer without the initial cost of a home computer, the on-going cost of maintenance, and the cost of upgrading hardware and software. The communication link can be a secure link.

Abstract translation: 为了向家庭用户提供具有成本效益的PC处理能力，家庭用户被提供有仅具有足够的处理能力的终端，以通过网络与服务提供商进行通信。 响应于来自家庭用户终端的请求，由服务提供商执行任何处理和程序执行，并将结果返回到终端。 除了处理能力之外，数据也存储在服务提供商中。 由于处理和数据存储由服务提供商执行，所以对程序和/或硬件的改变可以限于服务提供商的处理资源。 此外，服务提供商可以提供病毒和黑客保护，然后对家庭用户终端不需要保护。 以这种方式，家庭用户可以仅在实际使用的设施和软件的同时，在没有家用计算机的初始成本的情况下具有个人计算机的全部能力，正在进行的维护成本以及 升级硬件和软件的成本。 通信链路可以是一个安全的链路。

公开(公告)号：US07556442B2

公开(公告)日：2009-07-07

申请号：US11438772

申请日：2006-05-23

Applicant: Gene A. Frantz ,  Pascal Dorster

Inventor： Gene A. Frantz ,  Pascal Dorster

IPC: G03B17/00 ,  H04N5/225

CPC classification number: G03B7/26

Abstract: In an optical image acquisition and information transmission system, the system components can be fabricated, according to a first implementation, in a stack positioned on a circuit board. According to a second implementation, the system components are fabricated on a single substrate using the same semiconductor processes for each component. Both implementations result in better performance parameters. These systems are particularly useful as control devices wherein information resulting from processing the acquired image rather than the image itself is transmitted.

Abstract translation: 在光学图像采集和信息传输系统中，根据第一实施例，可以将系统部件制造在位于电路板上的堆叠中。 根据第二实施例，系统部件使用与每个部件相同的半导体工艺在单个基板上制造。 两种实现都会产生更好的性能参数。 这些系统作为控制装置特别有用，其中发送由处理所获取的图像而不是图像本身产生的信息。

公开(公告)号：US06738860B2

公开(公告)日：2004-05-18

申请号：US10449581

申请日：2003-05-30

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C800

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06735667B2

公开(公告)日：2004-05-11

申请号：US10449432

申请日：2003-05-30

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C800

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06732226B2

公开(公告)日：2004-05-04

申请号：US10452618

申请日：2003-06-02

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C804

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06732225B2

公开(公告)日：2004-05-04

申请号：US10452191

申请日：2003-06-02

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C804

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US6055268A

公开(公告)日：2000-04-25

申请号：US667267

申请日：1996-06-20

Applicant: William C. Timm ,  Walter Y. Chen ,  Gene A. Frantz ,  Domingo G. Garcia ,  Xiaolin Lu ,  Dennis G. Mannering ,  Michael O. Polley ,  Terence J. Riley ,  Donald P. Shaver ,  Song Wu ,  Alan Gatherer ,  Paul E. Schurr ,  Douglas B. Weiner

Inventor： William C. Timm ,  Walter Y. Chen ,  Gene A. Frantz ,  Domingo G. Garcia ,  Xiaolin Lu ,  Dennis G. Mannering ,  Michael O. Polley ,  Terence J. Riley ,  Donald P. Shaver ,  Song Wu ,  Alan Gatherer ,  Paul E. Schurr ,  Douglas B. Weiner

IPC: H04L29/10 ,  H04J11/00 ,  H04L1/00 ,  H04L1/16 ,  H04L5/14 ,  H04L25/03 ,  H04L25/49 ,  H04L27/26 ,  H04M11/00 ,  H04M11/06 ,  H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC classification number: H04L1/0023 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0016 ,  H04L25/03 ,  H04L25/03343 ,  H04L25/4921 ,  H04L27/2647 ,  H04L27/2649 ,  H04L27/2675 ,  H04L5/1438 ,  H04M11/06 ,  H04M11/062 ,  H04L1/0059 ,  H04L1/16 ,  H04L2025/03414 ,  H04L2025/03611 ,  Y02B60/31 ,  Y02B60/36

Abstract: A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm. A first embodiment utilizes a high speed digital programmable filter (1532). Another embodiment utilizes a data buffer (1533) which is periodically filled with data filtered by a digital signal processor (DSP).

Abstract translation: 具有接收和传输路径的调制解调器通信系统包括在传输路径中具有自适应滤波器（1532）的直接均衡器系统，以补偿通信信道的频率失真。 在由检测接收路径中的输入数据的数据检测器（1526）的控制下，发射机滤波器系数由滤波器系数计算器（1528）适配。 开关（1534）由发送输出数据缓冲器的状态控制，以将训练序列或输出数据复用到传输路径中。 当缓冲器空闲时，训练序列发生器（1540）链接到数模（D / A）转换器（1536）和线驱动器（1538）。 接收路径包括隔离开关（1520），接收放大器（1522）和限幅器（1524）。 接收器将接收到的训练序列与已知的训练序列进行相关，并使用诸如最小均方算法的自适应算法来更新均衡器滤波器系数。 第一实施例利用高速数字可编程滤波器（1532）。 另一个实施例利用周期性地填充由数字信号处理器（DSP）滤波的数据的数据缓冲器（1533）。

公开(公告)号：US5768205A

公开(公告)日：1998-06-16

申请号：US483002

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is desclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof as permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）被消除。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US5684753A

公开(公告)日：1997-11-04

申请号：US479297

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US5680370A

公开(公告)日：1997-10-21

申请号：US486168

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。