公开(公告)号：US5093807A

公开(公告)日：1992-03-03

申请号：US512611

申请日：1990-04-20

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John V. Moravec ,  Jean P. Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John V. Moravec ,  Jean P. Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 一种存储电路（14），其具有特别适于允许存储电路（14）用作视频帧存储器的特征。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US4624012A

公开(公告)日：1986-11-18

申请号：US375434

申请日：1982-05-06

Applicant: Kun-Shan Lin ,  Alva E. Henderson ,  Gene A. Frantz

Inventor： Kun-Shan Lin ,  Alva E. Henderson ,  Gene A. Frantz

IPC: G10L21/00 ,  G10L5/00

CPC classification number: G10L21/00

Abstract: Method and apparatus for converting voice characteristics of synthesized speech from a single applied source of synthesized speech in a manner obtaining modified voice characteristics pertaining to the apparent age and/or sex of the speaker. The apparatus is capable of altering the voice characteristics of synthesized speech to obtain modified voice sounds simulating child-like, teenage, adult, aged and sexual preference characteristics by control of vocal track parameters including pitch period, vocal tract model, and speech data rate. A source of synthesized speech having a predetermined pitch period, a predetermined vocal tract model, and a predetermined speech rate is separated into the respective speech parameters. The values of pitch, the speech data frame length, and the speech data rate are then varied in a preselected manner to modify the voice characteristics of the synthesized speech from the source thereof. Thereafter, the changed speech data parameters are re-combined into a modified synthesized speech data format having different voice characteristics with respect to the synthesized speech from the source, and an audio signal representative of human speech is generated from the modified synthesized speech data format from which audible synthesized speech may be generated.

Abstract translation: 从合成语音的单个应用源转换合成语音的语音特征的方法和装置，获得与演讲者的表观年龄和/或性别相关的修改的语音特征。 该装置能够通过控制包括音高周期，声道模型和语音数据速率在内的声道参数来改变合成语音的语音特征，从而获得模拟儿童，青少年，成人，年龄和性偏好特征的修改语音。 具有预定音调周期，预定声道模型和预定语音速率的合成语音源被分成各个语音参数。 然后，以预选的方式改变音调值，语音数据帧长度和语音数据速率，以从其源修改合成语音的语音特征。 此后，改变的语音数据参数被重新组合成相对于来自源的合成语音具有不同语音特征的修改的合成语音数据格式，并且从修改的合成语音数据格式生成代表人类语音的音频信号， 可以产生可听到的合成语音。

公开(公告)号：US06738860B2

公开(公告)日：2004-05-18

申请号：US10449581

申请日：2003-05-30

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C800

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06735667B2

公开(公告)日：2004-05-11

申请号：US10449432

申请日：2003-05-30

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C800

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06732226B2

公开(公告)日：2004-05-04

申请号：US10452618

申请日：2003-06-02

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C804

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06732225B2

公开(公告)日：2004-05-04

申请号：US10452191

申请日：2003-06-02

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C804

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US6055268A

公开(公告)日：2000-04-25

申请号：US667267

申请日：1996-06-20

Applicant: William C. Timm ,  Walter Y. Chen ,  Gene A. Frantz ,  Domingo G. Garcia ,  Xiaolin Lu ,  Dennis G. Mannering ,  Michael O. Polley ,  Terence J. Riley ,  Donald P. Shaver ,  Song Wu ,  Alan Gatherer ,  Paul E. Schurr ,  Douglas B. Weiner

Inventor： William C. Timm ,  Walter Y. Chen ,  Gene A. Frantz ,  Domingo G. Garcia ,  Xiaolin Lu ,  Dennis G. Mannering ,  Michael O. Polley ,  Terence J. Riley ,  Donald P. Shaver ,  Song Wu ,  Alan Gatherer ,  Paul E. Schurr ,  Douglas B. Weiner

IPC: H04L29/10 ,  H04J11/00 ,  H04L1/00 ,  H04L1/16 ,  H04L5/14 ,  H04L25/03 ,  H04L25/49 ,  H04L27/26 ,  H04M11/00 ,  H04M11/06 ,  H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC classification number: H04L1/0023 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0016 ,  H04L25/03 ,  H04L25/03343 ,  H04L25/4921 ,  H04L27/2647 ,  H04L27/2649 ,  H04L27/2675 ,  H04L5/1438 ,  H04M11/06 ,  H04M11/062 ,  H04L1/0059 ,  H04L1/16 ,  H04L2025/03414 ,  H04L2025/03611 ,  Y02B60/31 ,  Y02B60/36

Abstract: A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm. A first embodiment utilizes a high speed digital programmable filter (1532). Another embodiment utilizes a data buffer (1533) which is periodically filled with data filtered by a digital signal processor (DSP).

Abstract translation: 具有接收和传输路径的调制解调器通信系统包括在传输路径中具有自适应滤波器（1532）的直接均衡器系统，以补偿通信信道的频率失真。 在由检测接收路径中的输入数据的数据检测器（1526）的控制下，发射机滤波器系数由滤波器系数计算器（1528）适配。 开关（1534）由发送输出数据缓冲器的状态控制，以将训练序列或输出数据复用到传输路径中。 当缓冲器空闲时，训练序列发生器（1540）链接到数模（D / A）转换器（1536）和线驱动器（1538）。 接收路径包括隔离开关（1520），接收放大器（1522）和限幅器（1524）。 接收器将接收到的训练序列与已知的训练序列进行相关，并使用诸如最小均方算法的自适应算法来更新均衡器滤波器系数。 第一实施例利用高速数字可编程滤波器（1532）。 另一个实施例利用周期性地填充由数字信号处理器（DSP）滤波的数据的数据缓冲器（1533）。

公开(公告)号：US5768205A

公开(公告)日：1998-06-16

申请号：US483002

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is desclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof as permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）被消除。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US5684753A

公开(公告)日：1997-11-04

申请号：US479297

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US5680370A

公开(公告)日：1997-10-21

申请号：US486168

申请日：1995-06-07

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。