公开(公告)号：US20100211720A1

公开(公告)日：2010-08-19

申请号：US12458511

申请日：2009-07-14

申请人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester

发明人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester

IPC分类号： G06F13/00 ,  G06F13/36

CPC分类号： G11C7/10

摘要： Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable in the presence of an asserted transmission request from the associated source circuit to operate in combination with the arbitration circuits of other crossbar cells associated with the same data output path to re-use the bit lines of the data output path to detect the presence of multiple asserted transmission requests for the same data output path. In the event of such multiple asserted transmission requests, the arbitration circuitry operates in combination with the other arbitration circuits to implement a predetermined priority scheme to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between the multiple asserted transmission requests according to the predetermined priority scheme. Such a construction of crossbar circuitry enables a very efficient resolution of conflicts to be performed, whilst providing a very regular design, with uniform delay across all paths, and which requires significantly less control lines that typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars.

公开(公告)号：US07512820B2

公开(公告)日：2009-03-31

申请号：US11520007

申请日：2006-09-13

申请人： Krisztian Flautner ,  Trevor Nigel Mudge

发明人： Krisztian Flautner ,  Trevor Nigel Mudge

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3203 ,  Y02D10/126

摘要： Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.

摘要翻译： 通过使用多个性能请求计算算法来计算多个性能请求来执行性能级别选择，组合那些不同的性能请求以形成全局性能请求，然后根据全局性能级别请求选择性能级别。 可以将性能请求计算算法排列在层次结构中，其性能请求以从层次结构中的最低主导位置开始的序列进行评估，并且移动到层次结构中最主要的位置。 命令可以伴随每个性能级别请求来指定如何与其他性能级别请求组合。

公开(公告)号：US07337356B2

公开(公告)日：2008-02-26

申请号：US10896997

申请日：2004-07-23

申请人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Krisztian Flautner

发明人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Krisztian Flautner

IPC分类号： G06F11/00

CPC分类号： G06F11/1695 ,  G06F9/3861 ,  G06F9/3869 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024。 非延迟信号捕获元件1016在非延迟捕获时间捕获来自处理逻辑1014的输出。 在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。 误差检测电路1026和误差校正电路1028检测并校正延迟值中的随机误差，并将错误检测的延迟值提供给比较器1024。 比较器1024比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获得太早，应该被错误检查的延迟值替换。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

公开(公告)号：US08868817B2

公开(公告)日：2014-10-21

申请号：US13438920

申请日：2012-04-04

申请人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Dennis Michael Sylvester ,  Trevor Nigel Mudge

发明人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Dennis Michael Sylvester ,  Trevor Nigel Mudge

IPC分类号： G06F13/00 ,  G11C7/10 ,  G06F13/40 ,  H03K17/693

CPC分类号： G11C7/10 ,  G06F13/4022 ,  G06F2213/0038 ,  G11C7/1012 ,  H03K17/693

摘要： Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.

摘要翻译： 互连电路2具有连接到相应输入路径4的多个数据源电路8和连接到相应输出路径6的多个数据目的地电路10.连接单元12提供输入路径4和输出路径6之间的选择性连接。仲裁电路26 在不同输入路径上接收的重叠请求之间提供自适应优先级仲裁。 用于每个输出路径10的优先级位46的矩阵内的优先级位16用于表示竞争对该输出路径10的访问的不同输入路径之间的优先级关系。更新操作按照每行或每列进行应用 矩阵来实现更新计划，例如最近最近授予的，最近授予的，轮回，逆转，掉期，最少选择权，最近授予的选择权。

公开(公告)号：US08346832B2

公开(公告)日：2013-01-01

申请号：US11826996

申请日：2007-07-19

申请人： Trevor Nigel Mudge ,  David Theodore Blaauw ,  Carlos Alfonso Tokunaga

发明人： Trevor Nigel Mudge ,  David Theodore Blaauw ,  Carlos Alfonso Tokunaga

IPC分类号： G06F1/02 ,  G06F7/58

CPC分类号： G06F7/588 ,  H04L9/0866

摘要： A circuit for generating a random output value is disclosed that comprises: a bistable circuit having two stable states in which a 0 or a 1 is output and having a balanced metastable state in which a floating value between 0 and 1 is output, said bistable circuit resolving from said metastable state to one of said stable states on being switched on, said state depending on a voltage level at a port on said bistable circuit; a voltage level control circuit for controlling a voltage level at said port on said bistable circuit; a time measuring circuit for measuring a switching time taken for said bistable circuit to switch from said metastable state to one of said stable states following switch on; and control logic for controlling said time measuring circuit, said voltage level control circuit and a switching off and on of said bistable circuit, said control logic being adapted to perform a following sequence: control said voltage level control circuit to set a predetermined voltage level at said port on said bistable circuit, switch said bistable circuit on, detect a measured switching time, and turn said bistable circuit off and if said measured switching time is longer than a predetermined value, output said resolved stable state of said bistable circuit as said random output value.

摘要翻译： 公开了一种用于产生随机输出值的电路，包括：双稳态电路，具有两个稳定状态，其中输出0或1，并且具有输出浮点值在0和1之间的平衡亚稳态，所述双稳态电路 在所述稳定状态下从所述稳定状态分解成所述稳定状态之一被接通，所述状态取决于所述双稳态电路上的端口处的电压电平; 电压电平控制电路，用于控制所述双稳态电路上的所述端口处的电压电平; 时间测量电路，用于测量所述双稳态电路在接通之后从所述亚稳态转换到所述稳定状态之一所需的切换时间; 以及用于控制所述时间测量电路，所述电压电平控制电路和所述双稳态电路的断开和接通的控制逻辑，所述控制逻辑适于执行以下顺序：控制所述电压电平控制电路以将预定电压电平设置在 所述双稳态电路上的所述端口，打开所述双稳态电路，检测测量的开关时间，并关闭所述双稳态电路，如果所述测量的开关时间长于预定值，则将所述双稳态电路的所述分辨稳定状态输出为所述随机 产值。

公开(公告)号：US08255610B2

公开(公告)日：2012-08-28

申请号：US13137487

申请日：2011-08-19

申请人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester

发明人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester

IPC分类号： G06F13/00

CPC分类号： G11C7/10 ,  G11C7/1006 ,  H03K17/693

摘要： Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests.

公开(公告)号：US20110185260A1

公开(公告)日：2011-07-28

申请号：US13064601

申请日：2011-04-04

申请人： Trevor Nigel Mudge ,  Ganesh Suryanarayan Dasika ,  David Andrew Roberts

发明人： Trevor Nigel Mudge ,  Ganesh Suryanarayan Dasika ,  David Andrew Roberts

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1064

摘要： Data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks. A group data store stores data by grouping together blocks that have at least one faulty bit into groups of at least two blocks. For each group of blocks at least one of the blocks has a non-faulty bit for each of the bit locations in the blocks. A selector data store stores indicators for each group indicating which bits of the blocks within a group are the non-faulty bits. When storing data to a data block within a group, the data is stored in each of the blocks within the group. When retrieving data from a data block within a group, the data is read from respective bits of the blocks within the group as indicated by the indicators.

摘要翻译： 数据存储控制电路，用于控制将数据存储在数据块中的数据存储中的数据的存储和检索。 组数据存储器通过将具有至少一个故障位的块组合在一起至少组成两个块来存储数据。 对于每组块，至少一个块具有块中每个位位置的无故障位。 选择器数据存储器存储每个组的指示符，指示组内的块的哪些位是非故障位。 将数据存储到组内的数据块时，将数据存储在组内的每个块中。 当从组内的数据块检索数据时，从指示符指示的组内的块的各个比特中读取数据。

公开(公告)号：US07321942B2

公开(公告)日：2008-01-22

申请号：US10687924

申请日：2003-10-20

申请人： Krisztian Flautner ,  Trevor Nigel Mudge ,  David Walter Flynn

发明人： Krisztian Flautner ,  Trevor Nigel Mudge ,  David Walter Flynn

IPC分类号： G06F3/00

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A performance counter accumulates a value by periodically adding a variable increment value representing the amount of work performed. The increment value can be varied in dependence upon the processor clock frequency and may be adjusted under hardware and/or software control.

摘要翻译： 性能计数器通过周期性地添加表示所执行的工作量的可变增量值累加值。 增量值可以根据处理器时钟频率而变化，并且可以在硬件和/或软件控制下进行调整。

公开(公告)号：US07194385B2

公开(公告)日：2007-03-20

申请号：US10687928

申请日：2003-10-20

申请人： Krisztian Flautner ,  Trevor Nigel Mudge

发明人： Krisztian Flautner ,  Trevor Nigel Mudge

IPC分类号： G06F11/30

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A target processor performance level is calculated from a utilisation history of a processor in performance of a plurality of processing tasks. The method comprises calculating a task work value indicating processor utilisation in performing a given processing task within a predetermined task time-interval and calculating a target processor performance level in dependence upon the task work value.

摘要翻译： 在执行多个处理任务时，从处理器的利用历史计算目标处理器性能级别。 该方法包括：计算在预定任务时间间隔内执行给定处理任务的处理器利用率的任务工作值，并根据任务工作值计算目标处理器性能水平。

公开(公告)号：US07072229B2

公开(公告)日：2006-07-04

申请号：US11150585

申请日：2005-06-13

申请人： Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester ,  Krisztian Flautner

发明人： Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester ,  Krisztian Flautner

IPC分类号： G11C7/00

CPC分类号： G06F9/3869 ,  G06F9/3861 ,  G06F11/141 ,  G11C7/04 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/22 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2281

摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

摘要翻译： 提供了一种用于存储数据的存储器，包括：快速数据读取机构，用于从所述存储器读取数据值，以产生从所述存储器输出的快速读取结果用于进一步处理; 缓慢的数据读取机构，用于从所述存储器读取所述数据值，以产生在所述快速读取结果被输出以供进一步处理之后可用的慢速读取结果，所述慢速数据读取机构在读取所述数据值时不太容易出现所述数据值 快速数据读取机制; 比较器，用于比较所述快速读取结果和所述慢速读取结果，以检测所述快速读取结果是否与所述慢速读取结果不同; 如果所述比较器检测到所述快速读取结果不同于所述慢速读取结果以便使用所述快速读取结果抑制所述进一步处理，则输出所述慢速读取结果代替所述快速读取结果并重启所述进一步处理的错误修复逻辑 基于所述慢读取结果。