公开(公告)号：US07321942B2

公开(公告)日：2008-01-22

申请号：US10687924

申请日：2003-10-20

申请人： Krisztian Flautner ,  Trevor Nigel Mudge ,  David Walter Flynn

发明人： Krisztian Flautner ,  Trevor Nigel Mudge ,  David Walter Flynn

IPC分类号： G06F3/00

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A performance counter accumulates a value by periodically adding a variable increment value representing the amount of work performed. The increment value can be varied in dependence upon the processor clock frequency and may be adjusted under hardware and/or software control.

摘要翻译： 性能计数器通过周期性地添加表示所执行的工作量的可变增量值累加值。 增量值可以根据处理器时钟频率而变化，并且可以在硬件和/或软件控制下进行调整。

公开(公告)号：US20120286850A1

公开(公告)日：2012-11-15

申请号：US13067183

申请日：2011-05-13

申请人： James Edward Myers ,  John Philip Biggs ,  David Walter Flynn ,  Carsten Tradowsky

发明人： James Edward Myers ,  John Philip Biggs ,  David Walter Flynn ,  Carsten Tradowsky

IPC分类号： G11C5/14

CPC分类号： G11C14/0054

摘要： Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.

摘要翻译： 描述了以支持Z形电源门控的主从锁存器的形式存储数据值的装置。 在锁存器的输出处的NAND门52在保持模式期间迫使来自锁存器的输出处的预定保持信号值。 在锁存器的输入处的扫描多路复用器42在保持模式期间选择作为来自另一锁存器的预定保持信号的扫描输入。 在闩锁电源选通电路32内，使用虚拟电源轨VDDZ和VSSZ进行Z形电源门控，以减少漏电流。 状态存储电路34永久地连接到电源VDDG，VSSG，使得能够在保持模式期间保持其中存储的任何信号值。

公开(公告)号：US20120126879A1

公开(公告)日：2012-05-24

申请号：US12926531

申请日：2010-11-23

申请人： Bal S. Sandhu ,  Satchin Satish Idgunji ,  David Walter Flynn

发明人： Bal S. Sandhu ,  Satchin Satish Idgunji ,  David Walter Flynn

IPC分类号： H03K17/687

CPC分类号： H03K19/0008 ,  H03K17/145 ,  H03K19/00369 ,  H03K2017/066

摘要： A technique for controlling power gating in an integrated circuit is provided. The integrated circuit comprises a block of components to be power gated, and power gating circuitry for selectively isolating the block of components from the source voltage supply in order to achieve such power gating. Voltage regulator circuitry is used to provide a control voltage to the power gating circuitry when performing such power gating operations, the control voltage being settable to any of a plurality of predetermined voltage levels. An adaptive controller receives operating parameter data from either or both of the block of components and the power gating circuitry, that operating parameter data being indicative of leakage current. The adaptive controller then issues a feedback control signal to the voltage regulator circuitry whose value is dependent on the received operating parameter data. The voltage regulator circuitry is then responsive to the feedback control signal to change the control voltage between the plurality of predetermined voltage levels, until the operating parameter data indicates that a desired leakage current has been obtained within the power gating circuitry. Such an approach enables a balance to be achieved between reducing leakage current and reducing wear out of the power gating circuitry.

摘要翻译： 提供了一种用于控制集成电路中的电源门控的技术。 集成电路包括要被电源门控的组件块和用于选择性地将组件块与源电压供应隔离的电源门控电路，以便实现这种电源门控。 电压调节器电路用于在执行这种电源门控操作时向电源门控电路提供控制电压，该控制电压可设置为多个预定电压电平中的任何一个。 自适应控制器从组件块和功率选通电路中的一个或两个接收操作参数数据，该操作参数数据表示泄漏电流。 然后，自适应控制器向电压调节器电路发出反馈控制信号，该电压调节器电路的值取决于所接收的操作参数数据。 电压调节器电路然后响应于反馈控制信号来改变多个预定电压电平之间的控制电压，直到操作参数数据指示在电力门控电路内已经获得期望的泄漏电流。 这种方法使得能够在降低漏电流和减少电源门控电路之间的磨损的情况下实现平衡。

公开(公告)号：US07315796B2

公开(公告)日：2008-01-01

申请号：US11430903

申请日：2006-05-10

申请人： David Walter Flynn

发明人： David Walter Flynn

IPC分类号： G06F15/00

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

摘要： A processor 46 operating under program instruction control generates a desired performance level request. A mapping circuit then maps this to a control signal, such as a thermometer coded control signal, which is supplied to further circuits which require control so as to support the desired data processing performance level. These further circuits can include a clock generator 4 and a voltage controller 6.

摘要翻译： 在程序指令控制下操作的处理器46产生期望的性能等级请求。 然后，映射电路将其映射到诸如温度计编码控制信号的控制信号，其被提供给需要控制以支持期望的数据处理性能水平的另外的电路。 这些另外的电路可以包括时钟发生器4和电压控制器6。

公开(公告)号：US07206982B1

公开(公告)日：2007-04-17

申请号：US10868342

申请日：2004-06-16

申请人： Dipesh Ishwerbhai Patel ,  David Walter Flynn ,  Michael Peter Muller

发明人： Dipesh Ishwerbhai Patel ,  David Walter Flynn ,  Michael Peter Muller

IPC分类号： G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/3025

摘要： A diagnostic mechanism for an integrated circuit 2 uses a radio interface circuit 16 to provide communication between an external diagnostic device 22 and one or more diagnostic circuits 26, 28 within the integrated circuit 2. The use of a radio communication link for diagnostic data and control reduces the required pin count for the integrated circuit 2.

摘要翻译： 集成电路2的诊断机构使用无线电接口电路16来提供外部诊断装置22与集成电路2内的一个或多个诊断电路26,28之间的通信。 使用用于诊断数据和控制的无线电通信链路减少了集成电路2所需的引脚数。

公开(公告)号：US06345335B1

公开(公告)日：2002-02-05

申请号：US09394425

申请日：1999-09-13

申请人： David Walter Flynn

发明人： David Walter Flynn

IPC分类号： G06F1200

CPC分类号： G06F12/0853

摘要： A data processing system 2 is provided with a Harvard-type central processing unit 4 coupled to a first level memory 16. The first level memory 16 may be in the form of a cache memory. The first level memory 16 has a data access port and an instruction access port that support parallel data side and instruction side operations. A cache controller 62 may be provided to arbitrate between situations in which concurrent write operations to the same memory location are requested. A separate line fill port may be provided for cache line fills following a cache miss.

摘要翻译： 数据处理系统2具有耦合到第一级存储器16的哈佛式中央处理单元4.第一级存储器16可以是高速缓冲存储器的形式。 第一级存储器16具有支持并行数据侧和指令侧操作的数据访问端口和指令访问端口。 可以提供高速缓存控制器62以在请求同一存储器位置的并发写入操作的情况之间进行仲裁。 可以为高速缓存未命中的高速缓存行填充提供单独的行填充端口。

公开(公告)号：US5642479A

公开(公告)日：1997-06-24

申请号：US368837

申请日：1995-01-05

申请人： David Walter Flynn

发明人： David Walter Flynn

IPC分类号： G06F9/38 ,  G06F11/28 ,  G06F11/36 ,  G06F11/34

CPC分类号： G06F11/364

摘要： A data processing system is described in which trace signals are provided upon a trace bus 12 to track the address of an instruction code currently being executed and the latest address to which a data access was made. The system incorporates a central processing unit core 14 and an instruction pipeline 16 via which instruction codes are fed to the central processing unit core 14. When a non-sequential instruction code fetch is made, a number of cycles must pass before that non-sequential instruction has made its way along the instruction pipeline 16 to the central processing unit core 14. This period is utilised to output the address of the non-sequential instruction code fetch upon the trace bus. The multiple cycles available for this allow a time division multiplexing technique to be employed for different portions of the address thereby enabling the trace bus to be narrower. The same technique can be used to output data access addresses using time division multiplexing, but in this case a portion of the time taken to output the address overlaps with execution of some other instruction.

摘要翻译： 描述了一种数据处理系统，其中在跟踪总线12上提供跟踪信号以跟踪当前正在执行的指令码的地址和进行数据访问的最新地址。 该系统包括中央处理单元核心14和指令流水线16，通过该指令流水线指令代码被馈送到中央处理单元核心14.当进行非顺序指令代码提取时，多个周期必须经过该非顺序 指令已经沿着指令流水线16移动到中央处理单元核心14.该周期用于输出跟踪总线上非顺序指令代码获取的地址。 可用的多个周期允许对地址的不同部分采用时分复用技术，从而使跟踪总线更窄。 可以使用相同的技术来使用时分复用来输出数据访问地址，但是在这种情况下，输出地址所花费的时间的一部分与执行其他指令重叠。

公开(公告)号：US08665009B2

公开(公告)日：2014-03-04

申请号：US13562516

申请日：2012-07-31

申请人： James Edward Myers ,  Parameshwarappa Anand Kumar Savanth ,  David Walter Flynn ,  David William Howard ,  Bal S Sandhu

发明人： James Edward Myers ,  Parameshwarappa Anand Kumar Savanth ,  David Walter Flynn ,  David William Howard ,  Bal S Sandhu

IPC分类号： H01J19/82 ,  G11C5/14

CPC分类号： H02M3/07

摘要： An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry. This provides a particularly simple and effective mechanism for providing an additional load on the output node which can be altered with the aim of offsetting variation in the load on the output node presented by the circuit block, thus allowing the variation in the voltage output from the on-chip voltage generation circuitry to be controlled.

摘要翻译： 提供一种用于控制片上电压产生电路的电压输出变化的集成电路和方法。 集成电路包括电压产生电路，其被配置为从提供的输入电压进行操作，并且在输出节点处产生不同于所提供的输入电压的片上电压。 然后，电路块被布置成在电路块的操作期间接收由电压产生电路产生的片上电压源，该电路块在输出节点上呈现变化的负载。 振荡电路还耦合到输出节点以在输出节点上提供额外的负载，并且被配置为产生其频率随着片上电压供应的值变化而变化的振荡信号。 控制电路被配置为响应于触发条件来调节由振荡电路在输出节点上提供的附加负载。 这提供了一种特别简单和有效的机制，用于在输出节点上提供额外的负载，其可以被改变，目的是抵消由电路块呈现的输出节点上的负载的变化，从而允许来自 片上电压产生电路要被控制。

公开(公告)号：US08352819B2

公开(公告)日：2013-01-08

申请号：US12385674

申请日：2009-04-15

申请人： David Walter Flynn

发明人： David Walter Flynn

IPC分类号： H03M13/00

CPC分类号： G06F11/10 ,  G06F11/2236

摘要： A data processing apparatus is provided with state retention circuits into which state values are saved from nodes within the data processing circuitry when entering a sleep mode from an active mode. Error management circuitry is coupled to the state retention circuits and detects errors in the retention of the state values. If errors are detected then an error recover response is triggered. A voltage controller coupled to the error management circuitry serves to vary a supply voltage to the state retention circuits during the sleep mode so as to maintain a finite non-zero error rate in the retention of the state values by the state retention circuits.

摘要翻译： 数据处理装置设置有状态保持电路，当从活动模式进入睡眠模式时，状态保持电路从数据处理电路中的节点保存状态值。 错误管理电路耦合到状态保持电路，并检测状态值保持的错误。 如果检测到错误，则触发错误恢复响应。 耦合到误差管理电路的电压控制器用于在睡眠模式期间改变状态保持电路的电源电压，以便在状态保持电路保持状态值时保持有限的非零误码率。

公开(公告)号：US20110181343A1

公开(公告)日：2011-07-28

申请号：US12926498

申请日：2010-11-22

申请人： James Edward Myers ,  David Walter Flynn ,  John Philip Biggs

发明人： James Edward Myers ,  David Walter Flynn ,  John Philip Biggs

IPC分类号： H03K17/687 ,  H03K17/00 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/78 ,  H03K19/0016

摘要： A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device. A further data structure corresponding to a standard cell is provided comprising an overdriven retention switching device and a voltage switching device and yet a further standard cell data structure is provided comprising an overdriven voltage switching device.

摘要翻译： 提供了一种功率控制集成电路，其具有电压切换装置和保持开关装置，其具有来自过驱动电压源的输入，使得在保持使能配置中，保持开关装置相对于被耦合到并被驱动 从与电压切换装置相关联的电压输入信号。 提供过载保持开关装置作为与电压开关装置本身的单独实体，并且提供计算机可读存储介质，其存储包括标准单元电路定义的数据结构，用于生成验证集成的电路单元的电路布局 电路。 电路单元包括过驱动保持开关装置。 提供了与标准单元相对应的另外的数据结构，其包括过驱动保持开关装置和电压开关装置，并且还提供了包括过驱动电压开关装置的另外的标准单元数据结构。