公开(公告)号：US20070143515A1

公开(公告)日：2007-06-21

申请号：US11603091

申请日：2006-11-22

申请人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

发明人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

IPC分类号： G06F13/26

CPC分类号： G06F21/52 ,  G06F13/26

摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

摘要翻译： 中断控制器2设置有优先级寄存器6，优先级寄存器6存储优先级值P 0 -P 9，用于确定接收到的中断信号I 0至I 9之间的优先级。 优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。 以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问 所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。

公开(公告)号：US06708317B2

公开(公告)日：2004-03-16

申请号：US10023835

申请日：2001-12-21

申请人： Richard Roy Grisenthwaite

发明人： Richard Roy Grisenthwaite

IPC分类号： G06F1750

CPC分类号： G01R31/318357 ,  G01R31/318544 ,  G01R31/31922 ,  G01R31/31937 ,  G06F17/5022

摘要： A microprocessor core 4 is modeled using an obscured model 22 of the core functionality and a non-obscured model 24 of the scan chains that in that particular instance are associated with the microprocessor core 4. Validation of the design of a scan chain controller 12 can be achieved using the non-obscured scan chain model 24. Different scan chain models 24 can be relatively easily provided to model different scan chain physical configurations whilst leaving the more difficult to produce obscured core model 22 unaltered.

摘要翻译： 使用核心功能的模糊模型22和扫描链的非遮蔽模型24来模拟微处理器核心4，在特定情况下，微处理器核心4与微处理器核心4相关联。扫描链控制器12的设计的验证 可以使用非遮蔽的扫描链模型24来实现。可以相对容易地提供不同的扫描链模型24以模拟不同的扫描链物理配置，同时使难以产生模糊的核心模型22变得更加困难。

公开(公告)号：US09804851B2

公开(公告)日：2017-10-31

申请号：US13064257

申请日：2011-03-14

申请人： Richard Roy Grisenthwaite ,  David James Seal ,  Philippe Jean-Pierre Raphalen ,  Lee Douglas Smith

发明人： Richard Roy Grisenthwaite ,  David James Seal ,  Philippe Jean-Pierre Raphalen ,  Lee Douglas Smith

IPC分类号： G06F15/00 ,  G06F9/40 ,  G06F9/30 ,  G06F9/38 ,  G06F21/57 ,  G06F21/70

CPC分类号： G06F9/3016 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3861 ,  G06F21/577 ,  G06F21/70 ,  G06F2221/2145

摘要： A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

公开(公告)号：US09753724B2

公开(公告)日：2017-09-05

申请号：US13200348

申请日：2011-09-23

申请人： Simon John Craske ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

发明人： Simon John Craske ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30003 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

摘要： A data processing apparatus, method and computer program that perform an operation on one data element such as a register and conditionally select either that register or a further register on which no operation has been performed. The apparatus includes an instruction decoder configured to decode at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. Data processing operations are controlled by the instruction decoder and the data processor is responsive to the decoded at least one conditional select instruction where the condition does not have the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

公开(公告)号：US09092215B2

公开(公告)日：2015-07-28

申请号：US12929865

申请日：2011-02-22

申请人： Richard Roy Grisenthwaite ,  David James Seal

发明人： Richard Roy Grisenthwaite ,  David James Seal

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC分类号： G06F9/30112 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/384 ,  G06F9/3863

摘要： A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.

摘要翻译： 提供处理器4，其支持指定32位架构寄存器的第一指令集和指定64位架构寄存器的第二指令集。 这些指令集中的每一个都带有自己的一组架构寄存器供使用。 呈现给第一指令集的第一组寄存器具有与呈现给该第二指令集的第二组寄存器的一对一映射。 在硬件中提供的寄存器是64位寄存器。 在一些实施例中，当执行第一指令集的程序指令时，只有这些64位寄存器的最低有效部分被访问和操作，其中最重要的寄存器部分保持不变。 在第一指令集的指令内的寄存器指定字段与当前异常模式一起被解码以确定要使用的架构寄存器，而第二指令集使用寄存器指定字段而不依赖于异常模式来确定要使用哪个架构寄存器。

公开(公告)号：US08874883B2

公开(公告)日：2014-10-28

申请号：US13137208

申请日：2011-07-28

申请人： Michael John Williams ,  Richard Roy Grisenthwaite

发明人： Michael John Williams ,  Richard Roy Grisenthwaite

IPC分类号： G06F9/30 ,  G06F11/36

CPC分类号： G06F11/3648 ,  G06F9/30189

摘要： A data processing apparatus is provided comprising processing circuitry and instruction decoding circuitry. The data processing apparatus is capable of operating at a plurality of different privilege. Processing circuitry of the data processing apparatus imposes on program instructions different access permissions to at least one of a memory and a set of registers at different ones of the different privilege levels. A debug privilege-level switching instruction is provided and decoding circuitry is responsive to this instruction to switch the processing circuitry from a current privilege level to a target privilege level if the processing circuitry is in a debug mode. However, if the processing circuitry is in a non-debug mode the instruction decoding circuitry prevents execution of the privilege-level switching instruction regardless of the current privilege level.

摘要翻译： 提供了包括处理电路和指令解码电路的数据处理装置。 数据处理装置能够以多个不同的特权进行操作。 数据处理装置的处理电路对不同特权级别的存储器和一组寄存器中的至少一个对程序指令施加不同的访问权限。 提供调试权限级别切换指令，并且如果处理电路处于调试模式，则解码电路响应于该指令将处理电路从当前特权级别切换到目标特权级别。 然而，如果处理电路处于非调试模式，则指令解码电路防止执行特权级切换指令，而不管当前特权级别如何。

公开(公告)号：US08732400B2

公开(公告)日：2014-05-20

申请号：US12923725

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/00

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The interconnect circuitry comprises: at least one input for receiving transaction requests from the initiator device(s); at least one output for outputting transaction requests to the recipient device(s); a plurality of paths for transmitting said transaction requests between the at least one input and the at least one output; wherein at least one of said transaction requests comprises a data store maintenance request requesting a data store maintenance operation to be performed on data stores within the data processing apparatus; and control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to respond to receipt of the data store maintenance operation by transmitting the data store maintenance operation along at least one of the plurality of paths followed by a barrier transaction request, the control circuitry being configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along the at least one of said plurality of paths, such that at least some transaction requests subsequent to the data store maintenance request in the stream of transaction requests are held behind the data store maintenance request by the barrier transaction request.

摘要翻译： 公开了一种用于数据处理装置的互连电路。 互连电路被配置为提供数据路由，至少一个发起者设备可经由该路由访问至少一个接收者设备。 所述互连电路包括：用于接收来自所述发起者设备的交易请求的至少一个输入; 至少一个用于向所述接收方设备输出交易请求的输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的多条路径; 其中所述交易请求中的至少一个包括数据存储维护请求，请求在所述数据处理设备内的数据存储器上执行数据存储维护操作; 以及用于将所接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为通过沿着所述多个路径中的至少一个路径发送所述数据存储维护操作来响应于所述数据存储维护操作的接收，所述控制电路被配置为维持在 在沿所述多个路径中的至少一个路径传递的事务请求流内的至少一些关于屏障事务请求的事务请求，使得在事务请求流中的数据存储维护请求之后的至少一些事务请求是 通过屏障事务请求在数据存储维护请求之后。

公开(公告)号：US08677107B2

公开(公告)日：2014-03-18

申请号：US13064108

申请日：2011-03-07

申请人： Richard Roy Grisenthwaite

发明人： Richard Roy Grisenthwaite

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30101 ,  G06F9/30189

摘要： Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store 35. When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry 40 selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry 4. When the processing circuitry 4 is a further exception state, the stack pointer selection circuitry 40 selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.

摘要翻译： 处理电路4具有用于处理异常事件的多个异常状态EL0-EL3，异常状态包括基本电平异常状态EL0和至少一个进一步的电平异常状态EL1-EL3。 每个异常状态具有指示相应堆栈数据存储器35的存储器内的位置的相应堆栈指针。当处理电路处于基本电平异常状态EL0时，堆栈指针选择电路40选择基本电平堆栈指针作为当前堆栈 指示当前堆栈数据存储供处理电路4使用。当处理电路4是另外的异常状态时，堆栈指针选择电路40选择对应于当前进一步的基本级堆栈指针或进一步的级堆栈指针 级异常状态作为当前堆栈指针。

公开(公告)号：US20130205403A1

公开(公告)日：2013-08-08

申请号：US13368419

申请日：2012-02-08

申请人： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite

发明人： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite

IPC分类号： G06F21/24

CPC分类号： G06F21/52 ,  G06F9/30134 ,  G06F9/462 ,  G06F21/6245 ,  G06F2221/2105

摘要： A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level.

摘要翻译： 一种数据处理装置，包括用于执行数据处理的电路，多个寄存器; 以及包括具有不同安全级别的区域的数据存储器，至少一个安全区域（用于存储由安全域中操作的数据处理电路可访问并且不能由不安全域中操作的数据处理电路访问的敏感数据）和少于 安全区域（用于存储较不安全的数据）。 电路被配置为响应于正在执行的程序代码的存储位置来确定将数据存储到数据或从其加载数据。 响应于调用要执行的功能的程序代码，功能代码被存储在第二区域中，第二区域具有与第一区域不同的安全级别，数据处理电路被配置为确定第一和第二区域 具有较低的安全级别。

公开(公告)号：US08418175B2

公开(公告)日：2013-04-09

申请号：US12379082

申请日：2009-02-12

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F9/00

CPC分类号： G06F12/145

摘要： Processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system stores data for access by the processing circuitry and includes secure memory and non-secure memory . The secure memory is only accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. The hypervisor software sets a trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. The address translation circuitry can only cause the modified access request to be issued as a secure access request to the secure memory if the trusted identifier is set.

摘要翻译： 处理电路执行管理程序软件以支持在处理电路上执行多个虚拟机。 存储器系统存储用于由处理电路访问的数据，并且包括安全存储器和非安全存储器。 安全存储器只能通过安全访问请求访问。 地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定 物理地址。 如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信赖的虚拟机标识符。 如果设置了可信标识符，则地址转换电路只能使经修改的访问请求作为对安全存储器的安全访问请求发出。