Method for encoding information bit sequence in communication network

    公开(公告)号:US10666391B2

    公开(公告)日:2020-05-26

    申请号:US16249910

    申请日:2019-01-17

    Abstract: Embodiments of this application provide a method for encoding data in a wireless communication network. A communication device obtains an information bit sequence of a bit length K and a code length M. When M is greater than or equal to a first threshold and K is greater than or equal to a second threshold, the device divides the information bit sequence into p subsequences that are of an equal length K1. Then the device encodes each of the p subsequence to obtain p encoded subsequences. The device rate-matches each of the p encoded subsequences to obtain p rate matched subsequences, concatenates the p rate matched subsequences to obtain the output sequence of the code length M, then outputs the output sequence.

    Channel state information reporting method and communications apparatus

    公开(公告)号:US10601543B2

    公开(公告)日:2020-03-24

    申请号:US16540086

    申请日:2019-08-14

    Abstract: The application provides manner for communicating channel state information (CSI) in a communication network. A preset length is used for equalizing lengths of CSI to be reported. The preset length is determined based on a quantity of CSI-reference signal (RS) ports. A communication device determines whether a total length of one or more indication information items to be included in the CSI is less than the preset length. If the total length of the one or more indication information items to be included in the CSI is less than the preset length, the communication device adds one or more padding bits, to obtain a CSI bit sequence including the one or more indication information items and the one or more padding bits. A total length of the CSI bit sequence is consistent with the preset length. The communication device then outputs the CSI bit sequence.

    Method and device for parallel polar code encoding/decoding

    公开(公告)号:US10484130B2

    公开(公告)日:2019-11-19

    申请号:US15717745

    申请日:2017-09-27

    Abstract: Embodiments of this disclosure enhance the error detection performance of parallel polar encoding by cross-concatenating parity bits between segments of information bits transmitted over different sets of sub-channels. In one embodiment, a first segment of information bits is transmitted over a first set of sub-channels, and at least a second segment of information bits, and a masked parity bit, are transmitted over a second set of sub-channels. A value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits. The bitwise combination may be a bitwise AND, a bitwise OR, or a bitwise XOR of the respective parity bits.

    METHOD FOR ENCODING INFORMATION BIT SEQUENCE IN COMMUNICATION NETWORK

    公开(公告)号:US20190149268A1

    公开(公告)日:2019-05-16

    申请号:US16249910

    申请日:2019-01-17

    Abstract: Embodiments of this application provide a method for encoding data in a wireless communication network. A communication device obtains an information bit sequence of a bit length K and a code length M. When M is greater than or equal to a first threshold and K is greater than or equal to a second threshold, the device divides the information bit sequence into p subsequences that are of an equal length K1. Then the device encodes each of the p subsequence to obtain p encoded subsequences. The device rate-matches each of the p encoded subsequences to obtain p rate matched subsequences, concatenates the p rate matched subsequences to obtain the output sequence of the code length M, then outputs the output sequence.

    METHOD AND APPARATUS FOR A SUPERSCALAR PROCESSOR
    37.
    发明申请
    METHOD AND APPARATUS FOR A SUPERSCALAR PROCESSOR 审中-公开
    超级处理器的方法和装置

    公开(公告)号:US20160291980A1

    公开(公告)日:2016-10-06

    申请号:US14676461

    申请日:2015-04-01

    Inventor: Yiqun Ge Wuxian Shi

    Abstract: A superscalar processor, for out of order self-timed execution, comprising a plurality of independent self-timed function units, having corresponding instruction queues for holding instructions to be executed by the function unit. The processor further comprising an instruction dispatcher configured for inputting instructions in program counter order; and determining an appropriate function unit for execution of the instruction and a resource management unit configured for monitoring the function units and signaling availability of the appropriate function unit, wherein the dispatcher only dispatches the instruction to the appropriate function unit in response to the availability signal from the resource management unit.

    Abstract translation: 一种超标量处理器,用于无序自定时执行,包括多个独立的自定时功能单元,具有用于保持由功能单元执行的指令的相应指令队列。 所述处理器还包括配置成以程序计数器顺序输入指令的指令分配器; 以及确定用于执行所述指令的适当功能单元和被配置用于监视所述功能单元和所述适当功能单元的信令可用性的资源管理单元,其中所述调度员仅响应于来自所述功能单元的可用性信号将所述指令发送到所述适当的功能单元 资源管理单元。

    METHOD AND APPARATUS FOR DISTRIBUTED INFERENCE

    公开(公告)号:US20250088431A1

    公开(公告)日:2025-03-13

    申请号:US18901713

    申请日:2024-09-30

    Abstract: Aspects of the present disclosure relate to inference and, in particular, to distributed inference representative of a machine learning process. It is expected that inferencing will be a service in wireless networks. Aspects of the present application relate to applying aspects of coding theory to distributed inference to introduce redundancy. Methods of decoding outputs from a distributed inference process are also provided.

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